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m 1998 microchip technology inc. preliminary ds40181b-page 1 devices included in this data sheet: pic12ce673 pic12ce674 high-performance risc cpu: only 35 single word instructions to learn all instructions are single cycle (400 ns) except for program branches which are two-cycle operating speed: dc - 10 mhz clock input dc - 400 ns instruction cycle 14-bit wide instructions 8-bit wide data path interrupt capability special function hardware registers 8-level deep hardware stack direct, indirect and relative addressing modes for data and instructions peripheral features: four-channel, 8-bit a/d converter 8-bit real time clock/counter (tmr0) with 8-bit programmable prescaler interrupt on pin change (gp0, gp1, gp3) 1,000,000 erase/write cycle eeprom data memory eeprom data retention > 40 years device memory program data ram data eeprom pic12ce673 1024 x 14 128 x 8 16 x 8 pic12ce674 2048 x 14 128 x 8 16 x 8 pin diagram: special microcontroller features: in-circuit serial programming (icsp) internal 4 mhz oscillator with programmable calibration selectable clockout power-on reset (por) power-up timer (pwrt) and oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code protection power saving sleep mode internal pull-ups on i/o pins (gp0, gp1, gp3) internal pull-up on mclr pin selectable oscillator options: - intrc: precision internal 4 mhz oscillator - extrc: external low-cost rc oscillator - xt: standard crystal/resonator - hs: high speed crystal/resonator - lp: power saving, low frequency crystal cmos technology: low-power, high-speed cmos eprom/ eeprom technology fully static design wide operating voltage range 2.5v to 5.5v commercial, industrial, and extended temperature ranges low power consumption < 2 ma @ 5v, 4 mhz 15 m a typical @ 3v, 32 khz < 1 m a typical standby current pdip, windowed cerdip 8 7 6 5 1 2 3 4 pic12ce673 pic12ce674 gp5/osc1/clkin gp4/osc2/an3/clkout gp3/mclr /v pp v dd v ss gp0/an0 gp1/an1/v ref gp2/t0cki/an2/int 8-pin, 8-bit cmos microcontroller with a/d converter and eeprom data memory pic12ce67x
pic12ce67x ds40181b -page 2 preliminary 1998 microchip technology inc. t ab le of content s 1.0 general description ............................................................................................................................... ........................................ 3 2.0 pic12ce67x device varieties ............................................................................................................................... ........................ 5 3.0 architectural overview ............................................................................................................................... .................................... 7 4.0 memory organization ............................................................................................................................... .................................... 11 5.0 i/o port ............................................................................................................................... .......................................................... 25 6.0 eeprom peripheral operatio n ............................................................................................................................... .................... 27 7.0 timer0 module ............................................................................................................................... .............................................. 31 8.0 analog - to - digital converter (a/d ) module ............................................................................................................................... .... 37 9.0 special features of the cpu ............................................................................................................................... ........................ 45 10.0 instruction set summary ............................................................................................................................... ............................... 61 11.0 development support ............................................................................................................................... ................................... 75 12.0 electrical characteristics for pic1 2ce67x ............................................................................................................................... ... 81 13.0 dc and ac characteristics - pic12ce67x ............................................................................................................................... .. 99 14.0 packaging information ............................................................................................................................... ................................ 103 index ............................................................................................................................... ................................................................... 107 pic12ce67x product identification system ............................................................................................................................... ...... 113 t o our v alued customers most current data sheet t o obtain the most up-to-date v ersion of this data sheet, please chec k our w or ldwide w eb site at: http://www .microchip .com y ou can deter mine the v ersion of a data sheet b y e xamining its liter ature n umber f ound on the bottom outside cor ner of an y page . the last char acter of the liter ature n umber is the v ersion n umber . e .g., ds30000a is v ersion a of document ds30000. errata an err ata sheet ma y e xist f or current de vices , descr ibing minor oper ational diff erences (from the data sheet) and recommended w or karounds . as de vice/documentation issues become kno wn to us , w e will pub lish an err ata sheet. the err ata will specify the re vi- sion of silicon and re vision of document to which it applies . t o deter mine if an err ata sheet e xists f or a par ticular de vice , please chec k with one of the f ollo wing: microchip s w or ldwide w eb site; http://www .microchip .com y our local microchip sales of ce (see last page) the microchip cor por ate liter ature center ; u .s . f ax: (602) 786-7277 when contacting a sales of ce or the liter ature center , please specify which de vice , re vision of silicon and data sheet (include lit- er ature n umber) y ou are using. corrections to this data sheet w e constantly str iv e to impro v e the quality of all our products and documentation. w e ha v e spent a g reat deal of time to ensure that this document is correct. ho w e v er , w e realiz e that w e ma y ha v e missed a f e w things . if y ou nd an y inf or mation that is missing or appears in error , please: fill out and mail in the reader response f or m in the bac k of this data sheet. e-mail us at w ebmaster@microchip .com. w e appreciate y our assistance in making this a better document.
1998 microchip technology inc. preliminary ds40181b -page 3 pic12ce67x 1.0 general d es cription the pic12ce67x de vices are lo w-cost, high-perf or- mance , cmos , fully-static , 8-bit microcontroller with integ r ated analog-to-digital (a/d) con v er ter and eepr om data memor y in the pic12cexxx micro- controller f amily . all picmicro microcontrollers emplo y an adv anced risc architecture . the pic12c67x microcontrollers ha v e enhanced core f eatures , eight-le v el deep stac k, and m ultiple inter nal and e xter nal interr upt sources . the separ ate instr uction and data b uses of the har v ard architecture allo w a 14-bit wide instr uction w ord with the separ ate 8-bit wide data. the tw o stage instr uction pipeline allo ws all instr uctions to e x ecute in a single cycle , e xcept f or prog r am br anches which require tw o cycles . a total of 35 instr uctions (reduced instr uction set) are a v ailab le . additionally , a large register set giv es some of the architectur al inno v ations used to achie v e a v er y high perf or mance . pic12c67x microcontrollers typically achie v e a 2:1 code compression and a 4:1 speed impro v ement o v er other 8-bit microcontrollers in their class . the pic12ce67x de vices ha v e 128 b ytes of ram, 16 b ytes of eepr om data memor y , 5 i/o pins and 1 input pin. in addition a timer/counter is a v ailab le . also a 4- channel high-speed 8-bit a/d is pro vided. the 8-bit res- olution is ideally suited f or applications requir ing lo w- cost analog interf ace , e .g. ther mostat control, pressure sensing, etc. the pic12ce67x de vice has special f eatures to reduce e xter nal components , thus reducing cost, enhancing system reliability and reducing po w er con- sumption. t he p o w er-on reset (por), p o w er-up timer (pwr t), and oscillator star t-up timer (ost) eliminate the need f or e xter nal reset circuitr y . there are f iv e o scillator con gur ations to choose from, including intrc precision inter nal oscillator mode and the po w er-sa ving lp (lo w p o w er) oscillator mode . p o w er sa ving sleep mode , w atchdog timer and code protection f eatures impro v e system cost, po w er and reliability .the sleep (po w er-do wn) f eature pro vides a po w er sa ving mode . the user can w ak e up the chip from sleep through se v er al e xter nal and inter nal interr upts and resets . a highly reliab le w atchdog timer with its o wn on-chip rc oscillator pro vides protection against softw are loc k- up . a uv er asab le windo w ed pac kage v ersion is ideal f or code de v elopment while the cost-eff ectiv e one-time- prog r ammab le (o tp) v ersion is suitab le f or production in an y v olume . th e customer can tak e full adv antage of microchip s pr ice leadership in o tp microcontrollers while bene ting from the o tp s e xibility . the pic12ce67x de vice ts perf ectly in applications r anging from secur ity and remote sensors to appliance control and automotiv e . the epr om technology mak es customization of application prog r ams (tr ans- mitter codes , motor speeds , receiv er frequencies , etc.) e xtremely f ast and con v enient. the small f ootpr int pac kages mak e this microcontroller ser ies perf ect f or all applications with space limitations . lo w cost, lo w po w er , high perf or mance , ease of use and i/o e xibility mak e the pic12ce67x v er y v ersatile e v en in areas where no microcontroller use has been considered bef ore (e .g. timer functions , comm unications and coprocessor applications). 1.1 f amil y and upwar d compatibility the pic12ce67x products are compatib le with o ther members of the 14-bit, pic12c67x and pic16cxxx f amilies . 1.2 de vel opment suppor t the pic12ce67x de vice is suppor ted b y a full-f ea- tured macro assemb ler , a softw are sim ulator , an in-cir- cuit em ulator , a lo w-cost de v elopment prog r ammer and a full-f eatured prog r ammer . a ? compiler and fuzzy logic suppor t tools are also a v ailab le .
pic12ce67x ds40181b -page 4 preliminary 1998 microchip technology inc. t able 1-1: pic12cxxx & pic12cexxx f amil y of de vices pic12c508(a) pic12c509(a) pic12ce518 pic12ce519 pic12c671 pic12c672 pic12ce673 pic12ce674 clock maximum frequency of operation (mhz) 4 4 4 4 10 10 10 10 memory eprom program memory 512 x 12 1024 x 12 512 x 12 1024 x 12 1024 x 14 2048 x 14 1024 x 14 2048 x 14 ram data memory (bytes) 25 41 25 41 128 128 128 128 peripherals eeprom data memory (bytes) 16 16 16 16 timer module(s) tmr0 tmr0 tmr0 tmr0 tmr0 tmr0 tmr0 tmr0 a/d con- verter (8-bit) channels 4 4 4 4 features wake-up from sleep on pin change yes yes yes yes yes yes yes yes interrupt sources 4 4 4 4 i/o pins 5 5 5 5 5 5 5 5 input pins 1 1 1 1 1 1 1 1 internal pull-ups yes yes yes yes yes yes yes yes in-circuit serial programming yes yes yes yes yes yes yes yes number of instructions 33 33 33 33 35 35 35 35 packages 8-pin dip, jw, soic 8-pin dip, jw, soic 8-pin dip, jw, soic 8-pin dip, jw, soic 8-pin dip, jw, soic 8-pin dip, jw, soic 8-pin dip, jw 8-pin dip, jw all pic12cxxx & pic12cexxx de vices ha v e p o w er-on reset, selectab le w atchdog timer , selectab le code protect and high i/o current capability . all pic12cxxx & pic12cexxx de vices use ser ial prog r amming with data pin gp0 and cloc k pin gp1.
1998 microchip technology inc. preliminary ds40181b -page 5 pic12ce67x 2.0 pic12ce67x de vice v arieties a v ar iety of frequency r anges and pac kaging options are a v ailab le . depending on application and production requirements , the proper de vice option can be selected using the inf or mation in the pic12ce67x product iden- ti cation system section at the end of this data sheet. when placing orders , please use that p age of the data sheet to specify the correct par t n umber . f or e xample , the pic12c e 67x d e vice ?ype i s indi- cated in the de vice n umber : 1. ce , as in pic12 ce 67 4. these de vices ha v e o tp prog r am memor y , eepr om data memor y and oper ate o v er the standard v oltage r ange . 2.1 uv erasab le de vices the uv er asab le v ersion, off ered in windo w ed pac k- age , is optimal f or prototype de v elopment and pilot pro- g r ams . the uv er asab le v ersion can be er ased and repro- g r ammed to an y of the con gur ation modes . microchip's pi cs t ar t a p lus a nd pr o ma te a pro- g r ammers both suppor t the pic1 2ce67x. third par ty prog r ammers also are a v ailab le; ref er to the microchip third p ar ty guide f or a list of sources . 2.2 one-time-pr ogrammab le (o tp) de vices the a v ailability of o tp de vices is especially useful f or customers who need the e xibility f or frequent code updates and small v olume applications . the o tp de vices , pac kaged in plasti c p ac kages , per- mit the user to prog r am them once . i n addition to the prog r am memor y , the con gur ation bits m ust also be prog r ammed. note: please note that er asing the de vice will also er ase the pre- prog r ammed inter nal calibr ation v alue f or the inter nal oscillator . the calibr ation v alue m ust be sa v ed pr ior to e r asing the par t. 2.3 quic k-t urn-pr ogramming (qtp) de vices microchip o ff ers a qtp prog r amming ser vice f or f ac- tor y production orders . t his ser vice is made a v ailab le f or users who cho o se not to prog r am a medium to high quantity of units and whose code patter ns ha v e stabi- liz ed. t he de vices are identical to the o tp de vices b ut with all epr om locations and c on gur ation o ptions already prog r ammed b y the f actor y . cer tain code and prototype v er i cation procedures a pply bef ore produc- tion shipments are a v ailab le . please contact y our local microchip t echnology sales of ce f or more details . 2.4 serializ ed quic k-t urn pr ogramming (sqtp sm ) de vices microchip o ff ers a u nique prog r amming ser vice where a f e w user-de ned locations in each de vice are pro- g r ammed with diff erent ser ial n umbers . t he ser ial n um- bers ma y be r andom, pseudo-r andom, or sequential. ser ial prog r amming allo ws each de vice to ha v e a unique n umber which can ser v e as an entr y-code , pass w ord, or id n umber .
pic12ce67x ds40181b -page 6 preliminary 1998 microchip technology inc. no tes:
1998 microchip technology inc. preliminary ds40181b -page 7 pic12ce67x 3.0 ar c hitectural over vie w the high perf or mance of the pic12ce67x f amily can be attr ib uted to a n umber of architectur al f eatures com- monly f ound in risc microprocessors . t o begin with, the pic12ce67x uses a har v ard architecture , in which prog r am and data are accessed from separ ate memo- r ies using separ ate b uses . this impro v es bandwidth o v er tr aditional v on neumann architecture in which pro- g r am and data are f etched from the same memor y using the same b us . separ ating prog r am and data b uses also allo w instr uctions to be siz ed diff erently than the 8-bit wide data w ord. instr uction opcodes are 14- bit s wide making it possib le to ha v e all single w ord instr uctions . a 14-bit wide prog r am memor y access b us f etches a 14-bit instr uction in a single cycle . a tw o- stage pipeline o v er laps f etch and e x ecution of instr uc- tions ( example 3-1 ). consequently , all instr uctions ( 35 ) e x ecute in a single cycle ( 400 ns @ 10 mhz ) e xcept f or prog r am br anches . the tab le belo w lists prog r am memor y (epr om), data memor y (ram), and non-v olatile memor y (eepr om) f or each pic12ce67x de vice . de vice pr ogram memor y ram data memor y eepr om data memor y pic12ce673 1k x 14 128 x 8 16x8 pic12ce674 2k x 14 128 x 8 16x8 the pic12ce67x can directly or indirectly address its register les or data memor y . all special function regis- ters , including the prog r am counter , are mapped in the data memor y . the pic12ce67x has an or thogonal (symmetr ical) instr uction set that mak es it possib le to carr y out an y oper ation on an y register using an y addressing mode . this symmetr ical nature and lac k of ?pecial optimal situations mak e prog r amming with the pic12ce67x simple y et ef cient. in addition, the lear n- ing cur v e is reduced signi cantly . pic12ce67x de vices contain an 8-bit alu and w or k- ing register . the alu is a gener al pur pose ar ithmetic unit. it perf or ms ar ithmetic and boolean functions betw een the data in the w or king register and an y regis- ter le . the alu is 8-bits wide and capab le of addition, sub- tr action, shift and logical oper ations . unless otherwise mentioned, ar ithmetic oper ations are tw o's comple- ment in nature . in tw o-oper and instr uctions , typically one oper and is the w or king register (w register). the other oper and is a le register or an immediate con- stant. in single oper and instr uctions , the oper and is either the w register or a le register . the w register is an 8-bit w or king register used f or alu oper ations . it is not an addressab le register . depending on the instr uction e x ecuted, the alu ma y aff ect the v alues of the carr y (c), digit carr y (dc), and zero (z) bits in the st a tus register . the c and dc bits oper ate as a borro w bit and a digit borro w out bit, respectiv ely , in subtr action. see the sublw and subwf instr uctions f or e xamples .
pic12ce67x ds40181b -page 8 preliminary 1998 microchip technology inc. figure 3-1: p ic12ce67x bloc k dia gr a m p o w er-up timer oscillator star t-up timer epr om prog r am memor y 13 data bus 8 14 prog r am bus instr uction reg prog r am counter ram file registers direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg st a tus reg mux alu w reg instr uction decode & control timing gener ation osc1/clkin osc2 /clk out mclr v dd , v ss timer0 gpio 8 8 gp4/osc2/an3 /clk out gp3/ mclr /vpp gp2 /t0cki/an2 /int gp1/an1/v ref gp0/an0 8 3 gp5/osc1/clkin 8 le v el stac k (13 bit) 128 b ytes note 1: higher order bits are from the st a tus register . a/d w atchdog timer p o w er-on reset de vice pic12ce673 pic12ce674 pr ogram memor y data memor y (ram) 1k x 14 2k x 14 12 8 x 8 12 8 x 8 4 mhz cloc k inter nal non-v olatile memor y (eepr om) 16 x 8 16 x 8 data memor y 16x8 eepr om scl sd a
1998 microchip technology inc. preliminary ds40181b -page 9 pic12ce67x t ab le 3-1: pic12ce67x pinout description name dip pin # i/o/p t ype buff er t ype description gp0/an0 7 i/o ttl/st bi-directional i/o por t/ser ial prog r amming d at a/ analog input 0. can be softw are prog r ammed f or inter nal w eak pull-up and interr upt o n pin change . this b uff er is a schmitt t r igger input when used in ser ial prog r amming mode . gp1/an1/v ref 6 i/o ttl/st bi-directional i/o por t/ser ial prog r amming cl oc k/ analog input 1/v oltage ref erence . can be softw are prog r ammed f or inter nal w eak pull-up and interr upt o n pin change . this b uff er is a schmitt t r igger input when used in ser ial pro- g r amming mode . gp2 /t0cki/an2 /int 5 i/o st bi-directional i/o por t/analog input 2. can be con gured as t0cki or e xt er nal interr upt . gp3/ mclr /v pp 4 i ttl /st input por t/master clear (reset) input/prog r amming v oltage input. when con gured as mclr , this pin is an activ e lo w reset to the de vice . v oltage on mclr /v pp m u st not e xceed v dd dur ing nor mal de vice oper ation. ca n be softw are pro- g r ammed f or inter nal w eak pull-up and interr upt o n pin change . w eak pull-up alw a ys on if con gured as mclr . this b uff er is schmitt t r igger when in mclr mode . gp4/osc2/an3 / clk ou t 3 i/o ttl bi-directional i/o por t/oscillator cr ystal output/analog input 3. connections to cr ystal or resonator in cr ystal oscillator mode ( hs , xt and lp modes only , gpio in other modes). in extrc and intrc modes , th e pin output can be con g- ured to clk out which has 1/4 the frequency of osc1 and denotes the instr uction cycle r ate . gp5/osc1/clkin 2 i /o ttl/st bidirectional io por t /o scillator cr ystal input/e xter nal cloc k source input (gpio in intrc mode only , osc1 in all other oscillator modes). schmitt tr igger in extrc mode only . v dd 1 p p ositiv e supply f or logic and i/o pins v ss 8 p ground ref erence f or logic and i/o pins legend: i = input, o = output, i/o = input/output, p = po w er , ?= not used, ttl = ttl input, st = schmitt t r igger input
pic12ce67x ds40181b -page 10 preliminary 1998 microchip technology inc. figure 3-2: cloc k/instruction cyc le example 3-1: instruction pipeline flo w q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clk out (extrc and pc pc+1 pc+2 f etch inst (pc) ex ecute inst (pc-1) f etch inst (pc+1) ex ecute inst (pc) f etch inst (pc+2) ex ecute inst (pc+1) inter nal phase cloc k intrc modes) all instr uctions are single cycle , e xcept f or an y prog r am br anches . these tak e tw o cycles since the f etch instr uc- tion is ushed from the pipeline while the ne w instr uction is being f etched and then e x ecuted. tcy0 tcy1 tcy2 tcy3 tcy4 tcy5 1. movlw 55h f etch 1 ex ecute 1 2. movwf gpio f etch 2 ex ecute 2 3. call sub_1 f etch 3 ex ecute 3 4. bsf gpio, bit3 (forced nop) f etch 4 flush 5. instruction @ address sub_1 f etch sub_1 ex ecute sub_1 3.1 cloc king sc heme/ instruction cyc le the cloc k input (from osc1) is inter nally divided b y f our to gener ate f our non-o v er lapping quadr ature cloc ks namely q1, q2, q3 and q4. inter nally , the pro- g r am counter (pc) is incremented e v er y q1, the instr uction is f etched from the prog r am memor y and latched into the instr uction register in q4. the instr uc- tion is decoded and e x ecuted dur ing the f ollo wing q1 through q4. the cloc ks and instr uction e x ecution o w is sho wn in figure 3-2 . 3.2 instruction flo w/pipelining an ?nstr uction cycle consists of f our q cycles (q1, q2, q3 and q4). the instr uction f etch and e x ecute are pipelined such that f etch tak es one instr uction cycle while decode and e x ecute tak es another instr uction cycle . ho w e v er , due to the pipelining, each instr uction eff ectiv ely e x ecutes in one cycle . if an instr uction causes the prog r am counter to change (e .g. goto ) then tw o cycles are required to complete the instr uction ( example 3-1 ). a f etch cycle begins with the prog r am counter (pc) incrementing in q1. in the e x ecution cycle , the f etched instr uction is latched into the ?nstr uction register " (ir) i n cycle q1. this instr uction is then decoded and e x ecuted dur ing the q2, q3, and q4 cycles . data memor y is read dur ing q2 (oper and read) and wr itten dur ing q4 (destination wr ite).
1998 microchip technology inc. preliminary ds40181b -page 11 pic12ce67x 4.0 memor y or ganization 4.1 pr ogram memor y or ganization the pic12ce67x has a 13-bit prog r am counter capa- b le of addressing an 8k x 14 prog r am memor y space . f or the pic12c e 67 3 the rst 1k x 14 (0000h-03ffh) is implemented. f or the pic12ce674 , t he rst 2k x 14 (0000h-07ffh) is implemented. accessing a location abo v e the ph ysi- cally implemented address will cause a wr aparound. the reset v ector is at 0000h and the interr upt v ector is at 0004h . figure 4-1: pic12ce67x pr ogram memor y map and stac k pc<12:0> 13 0000h 0004h 0005h 07ffh 1fffh stac k le v el 1 stac k le v el 8 reset v ector interr upt v ector on-chip prog r am memor y call, return retfie, retlw 0800h 0400h 03ffh p er ipher al (pic12ce674 only) 4.2 data memor y or ganization the data memor y i s par titioned into tw o banks which contain the gener al pur pose registe rs and the special function registers . bit rp0 is the bank select bit. rp0 (st a tus<5>) = 1 ? bank 1 rp0 (st a tus<5>) = 0 ? bank 0 each bank e xtends up to 7fh (128 b ytes). the lo w er locations of each bank are reser v ed f or the special function registers . abo v e the special function regis- ters are gener al pur pose registers implemented as static ram. both bank 0 and bank 1 contain special function registers . some "high use" special function registers from bank 0 are mirrored in bank 1 f or code reduction and quic k er access . also note that f0h through ffh on the pic12ce67x is mapped into bank 0 registers 70h-7fh as common ram . 4.2.1 gener al pur pose register file the register le can be a ccessed either directly , or indi- rectly through the file select r egister fsr ( section 4.5 ).
pic12ce67x ds40181b -page 12 preliminary 1998 microchip technology inc. figure 4-2: pic12ce67x r e g ister file map indf (1) tmr0 pcl st a tus fsr gpio pcla th intcon pir1 adres adcon0 indf (1) option pcl st a tus fsr tris pcla th intcon pie1 pcon adcon1 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1 fh 80 h 81 h 82 h 83 h 84 h 85 h 86 h 87 h 88 h 89 h 8a h 8b h 8c h 8d h 8e h 8f h 90 h 91 h 92 h 93 h 94 h 95 h 96 h 97 h 98 h 99 h 9a h 9b h 9c h 9d h 9e h 9f h 20 h a0 h gener al pur pose register gener al pur pose register 7f h ff h bank 0 bank 1 file address bf h c0 h unimplemented data memor y locations , read as '0'. note 1: not a ph ysical register . file address osccal f 0h efh mapped in bank 0 7 0h 4.2.2 special function registers the special function registers are registers used b y the cpu and p er ipher al modules f or controlling the desired oper ation of the de vice . these registers are implemented as s tatic ram. the special function registers can be classi ed into tw o sets (core and per ipher al). those registers associated with the ?ore functions are descr ibed in this section, and those related to the oper ation of the per ipher a l f eatures are descr ibed in the section of that per ipher al f eature .
1998 microchip technology inc. preliminary ds40181b -page 13 pic12ce67x t ab le 4-1: pic12ce67x special functio n register summar y ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on p o wer -on r eset v alue o n all other r eset s (3) bank 0 00h (1) indf addressing this location uses contents of fsr to address data memor y (not a ph ysical register) 0000 0000 0000 0000 01h tmr0 timer0 module s register xxxx xxxx uuuu uuuu 02h (1) pcl prog r am counter's (pc) least signi cant byte 0000 0000 0000 0000 03h (1) st a tus irp (4) rp1 (4) rp0 t o pd z dc c 0001 1xxx 000q quuu 04h (1) fsr indirect data memor y address pointer xxxx xxxx uuuu uuuu 05h gpio scl sd a gp5 gp4 gp3 gp2 gp1 gp0 11xx xxxx 11uu uuuu 06h unimplemented 07h unimplemented 08h unimplemented 09h unimplemented 0ah (1,2) pcla th wr ite buff er f or the upper 5 bits of the prog r am counter ---0 0000 ---0 0000 0bh (1) intcon gie peie t0ie inte gpi e t0if intf gpi f 0000 000x 0000 000u 0ch pir1 adif -0-- ---- -0-- ---- 0dh unimplemented 0eh unimplemented 0fh unimplemented 10h unimplemented 11h unimplemented 12h unimplemented 13h unimplemented 14h unimplemented 15h unimplemented 16h unimplemented 17h unimplemented 18h unimplemented 19h unimplemented 1ah unimplemented 1bh unimplemented 1ch unimplemented 1dh unimplemented 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 r chs1 chs0 go/ done r adon 00 00 00 00 00 00 00 00 legend: x = unkno wn, u = unchanged, q = v alue depends on condition, - = unimplemented read as '0', r = reser v ed. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper b yte of the prog r am counter is not directly accessib le . pcla th is a holding register f or the pc<12:8> whose contents are tr ansf erred to the upper b yte of the prog r am counter . 3: other (non po w er-up) resets include e xter nal reset through mclr and w atchdog timer reset. 4: the irp and rp1 bits are reser v ed on the pic12ce67x, alw a ys maintain these bits clear .
pic12ce67x ds40181b -page 14 preliminary 1998 microchip technology inc. bank 1 80h (1) indf addressing this location uses contents of fsr to address data memor y (not a ph ysical register) 0000 0000 0000 0000 81h option gppu intedg t0cs t0se psa ps2 ps1 ps0 11 11 1111 11 11 1111 82h (1) pcl prog r am counter's (pc) least signi cant byte 0000 0000 0000 0000 83h (1) st a tus irp (4) rp1 (4) rp0 t o pd z dc c 0001 1xxx 000q quuu 84h (1) fsr indirect data memor y address pointer xxxx xxxx uuuu uuuu 85h tris gpi o d ata direction register 0011 1111 0011 1111 86h unimplemented 87h unimplemented 88h unimplemented 89h unimplemented 8ah (1,2) pcla th wr ite buff er f or the upper 5 bits of the pc ---0 0000 ---0 0000 8bh (1) intcon gie peie t0ie inte gpi e t0if intf gpi f 0000 000x 0000 000 u 8ch pie1 adie -0-- ---- -0-- ---- 8dh unimplemented 8eh pcon por ---- --0- ---- --u- 8fh osccal cal5 cal4 cal3 cal2 cal1 cal0 1000 00-- uuuu uu-- 90h unimplemented 91h unimplemented 92h unimplemented 93h unimplemented 94h unimplemented 95h unimplemented 96h unimplemented 97h unimplemented 98h unimplemented 99h unimplemented 9ah unimplemented 9bh unimplemented 9ch unimplemented 9dh unimplemented 9eh unimplemented 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 t ab le 4-1: pic12ce67x special functio n register summar y (cont.) ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on p o wer -on r eset v alue o n all other r eset s (3) legend: x = unkno wn, u = unchanged, q = v alue depends on condition, - = unimplemented read as '0', r = reser v ed. shaded locations are unimplemented, read as ?? note 1: these registers can be addressed from either bank. 2: the upper b yte of the prog r am counter is not directly accessib le . pcla th is a holding register f or the pc<12:8> whose contents are tr ansf erred to the upper b yte of the prog r am counter . 3: other (non po w er-up) resets include e xter nal reset through mclr and w atchdog timer reset. 4: the irp and rp1 bits are reser v ed on the pic12ce67x, alw a ys maintain these bits clear .
1998 microchip technology inc. preliminary ds40181b -page 15 pic12ce67x 4.2.2.1 st a tus register the st a tus register , sho wn in figure 4-3 , contains the ar ithmetic status of the alu , the reset status and the bank select bits f or data memor y . the st a tus register can be the destination f or an y instr uction, as with an y other register . if the st a tus register is the destination f or an instr uction that aff ects the z, dc or c bits , then the wr ite to these three bits is disab led. these bits are set or cleared according to the de vice logic. fur ther more , the t o and pd bits are not wr itab le . theref ore , the result of an instr uction with the st a tus register as destination ma y be diff erent than intended. f or e xample , clrf status will clear the upper-three bits and set the z bit. this lea v es the st a tus register as 000u u1uu (where u = unchanged). it is recommended, theref ore , that only bcf, bsf, swapf and movwf instr uctions are used to alter the st a tus register because these instr uctions do not aff ect the z, c or dc bits from the st a tus register . f or other instr uctions , not aff ecting an y status bits , s ee the "i nstr uction set summar y ." note 1: bits irp and rp1 (st a tus<7:6>) are not used b y the pic12ce67x and should be maintained clear . use of these bits as gener al pur pose r/w bits is no t recom- mended, since this ma y aff ect upw ard compatibility with future products . note 2: the c and dc bits oper ate as a borro w and digit borro w bit, respectiv ely , in sub- tr action. see the sublw and subwf instr uctions f or e xamples . figure 4-3: status r egi ster (ad dress 03 h , 83 h ) reser v ed reser v ed r/ w -0 r -1 r -1 r/w -x r/w -x r/w -x irp rp1 rp0 t o pd z dc c r = readab le bit w = wr itab le bit u = unimplemented bit, re ad as ? - n = v alue at por reset bit7 bit0 bit 7: irp: register bank select bit (used f or indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ff h ) the irp bit is reser v ed, alw a ys maintain this bit clear . bit 6-5: rp1:rp0: register bank select bits (used f or direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 b ytes . the rp1 bit is reser v ed, alw a ys maintain this bit clear . bit 4: t o : time-out bit 1 = after po w er-up , clrwdt instr uction, or sleep instr uction 0 = a wdt time-out occurred bit 3: pd : p o w er-do wn bit 1 = after po w er-up or b y the clrwdt instr uction 0 = by e x ecution of the sleep instr uction bit 2: z : zero bit 1 = the result of an ar ithmetic or logic oper ation is z ero 0 = the result of an ar ithmetic or logic oper ation is not z ero bit 1: dc: digit carr y/ borro w bit ( addwf , addlw,sublw,subwf instr uctions)(f or borro w the polar ity is re v ersed) 1 = a carr y-out from the 4th lo w order bit of the result occurred 0 = no carr y-out from the 4th lo w order bit of the resul t bit 0: c: carr y/ borro w bit ( addwf , addlw,sublw,subwf instr uctions) 1 = a carr y-out from the most signi cant bit of the result occurre d 0 = no carr y-out from the most signi cant bit of the result occurred note: f o r borro w the polar ity is re v ersed. a subtr action is e x ecuted b y adding the tw o s complement of the second oper and. f or rotate ( rrf , rlf ) instr uctions , this bit is loaded with either the high or lo w order bit of the source register .
pic12ce67x ds40181b -page 16 preliminary 1998 microchip technology inc. 4.2.2.2 option register the option register i s a readab le and wr itab le regis- ter which contains v ar ious control bits to con gure the tmr0/wdt prescaler , the exter nal int inter r upt, tmr0, and the w eak pull-ups on gpio . note: t o achie v e a 1:1 prescaler assignment f or the tmr0 register , assign the prescaler to the w atchdog timer b y setting bit psa (option<3>). figure 4-4: optio n register (ad dress 81 h ) r/ w -1 r/w - 1 r/w - 1 r/w -1 r/w - 1 r/w - 1 r/w -1 r/w - 1 gppu intedg t0cs t0se psa ps2 ps1 ps0 r = readab le bit w = wr itab le bit u = unimplemented bit, re ad as ? - n = v alue at por reset bit7 bit0 bit 7: gppu : w eak pullup enab le 1 = w eak pullups disab led 0 = w eak pullups enab led (gp0, gp1, gp3) bit 6: intedg: interr upt edge 1 = interr upt on r ising edge of gp2/ t0cki/an2/int p in 0 = interr upt on f alling edge of gp2/ t0cki/an2/int p in bit 5 : t0cs: tmr0 cloc k source select bit 1 = t r ansition on gp2/t0cki/an2 /int pin 0 = inter nal instr uction cycle cloc k (clk out) bit 4: t0se: tmr0 source edge select bit 1 = increment on high-to-lo w tr ansition on gp2/t0cki/an2 /int pin 0 = increment on lo w-to-high tr ansition on gp2/t0cki/an2 /int pin bit 3: psa: prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0: ps2:ps0 : prescaler rate sel ect bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit v alue tmr0 rate wdt rate
1998 microchip technology inc. preliminary ds40181b -page 17 pic12ce67x 4.2.2.3 intcon register the intcon register is a readab le and wr itab le regis- ter which contains v ar ious enab le and ag bits f or the tmr0 register o v er o w , gpio p o r t change and exter- nal gp2/ int pin interr upts . note: interr upt ag bits get set when an interr upt condition occurs regardless of the state of its corresponding enab le bit or the global enab le bit, gie (intcon<7>). figure 4-5: i ntcon register (ad dress 0b h , 8b h ) r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -x gie peie t0ie inte gpie t0if intf gpif r = readab le bit w = wr itab le bit u = unimplemented bit, re ad as ? - n = v alue at por reset bit7 bit0 bit 7: gie: global interr upt enab le bit 1 = enab les all un-mask ed interr upts 0 = disab les all interr upts bit 6: peie: p er ipher al interr upt enab le bit 1 = enab les all un-mask ed per i pher al interr upts 0 = disab les all per ipher al interr upts bit 5: t0ie: tmr0 ov er o w interr upt enab le bit 1 = enab les the tmr0 interr upt 0 = disab les the tmr0 interr upt bit 4 : inte : int exter nal interr upt enab le bit 1 = enab les the e xter nal interr upt on gp2/int /t0cki/an2 pin 0 = disab les the e xter nal interr upt on gp2/int /t0cki/an2 pin bit 3 : gpie: gpio interr upt on change enab le bit 1 = enab les the gpio interr upt on change 0 = disab les the gpio interr upt on change bit 2: t0if: tmr0 ov er o w interr upt flag bit 1 = tmr0 register has o v er o w ed (m ust be cleared in softw are) 0 = tmr0 register did not o v er o w bit 1 : intf : int exter nal interr upt flag bit 1 = the e x ter nal interr upt on gp2/int /t0cki/an2 pin occurred ( m ust be cleared in softw are) 0 = the e xter nal interr upt on gp2/int /t0cki/an2 pin did not occur bit 0 : gpif: gpio interr upt on change flag bit 1 = gp0, gp1, or gp3 pins changed state (m ust be cleared in softw are) 0 = neither gp0, gp1, nor gp3 pins ha v e changed state
pic12ce67x ds40181b -page 18 preliminary 1998 microchip technology inc. 4.2.2.4 pie1 register this register contains the individual enab le bits f or the p er ipher al interr upts . note: bit peie ( intcon<6> ) m ust be set to enab le an y per ipher al interr upt. figure 4-6: pie1 registe r (ad dress 8c h ) u- 0 r/w -0 u- 0 u- 0 u- 0 u- 0 u- 0 u- 0 adie r = readab le bit w = wr itab le bit u = unimplemented bit, re ad as ? - n = v alue at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6: adie: a/d con v er ter interr upt enab le bit 1 = enab les the a/d interr upt 0 = disab les the a/d interr upt bit 5-0: unimplemented: read as '0'
1998 microchip technology inc. preliminary ds40181b -page 19 pic12ce67x 4.2.2.5 pir1 register this r egister contains the individual ag bits f or the p er ipher al interr upts . note: interr upt ag bits get set when an interr upt condition occurs regardless of the state of its corresponding enab le bit or the global enab le bit, gie (intcon<7>). user soft- w are should ensure the appropr iate inter- r upt ag bits are clear pr ior to enab ling an interr upt. figure 4-7: pir1 registe r (ad dress 0c h ) u- 0 r/w -0 u- 0 u- 0 u- 0 u- 0 u- 0 u- 0 adif r = readab le bit w = wr itab le bit u = unimplemented bit, re ad as ? - n = v alue at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6: adif: a/d con v er ter interr upt flag bit 1 = an a/d con v ersion completed 0 = the a/d con v ersion is not complete bit 5-0: unimplemented: read as '0'
pic12ce67x ds40181b -page 20 preliminary 1998 microchip technology inc. 4.2.2.6 pcon register the p o w er control (pcon) register contains a ag bit to allo w diff erentiation betw een a p o w er-on reset (por), an e xter nal mclr reset, and wdt reset . figure 4-8: pcon regi ster (ad dress 8e h ) u-0 u-0 u-0 u-0 u-0 u-0 r/w -0 u-0 por r = readab le bit w = wr itab le bit u = unimplemented bit, re ad as ? - n = v alue at por reset bit7 bit0 bit 7-2: unimplemented: read as '0' bit 1: por : p o w er-on reset status bit 1 = no p o w er-on reset occurred 0 = a p o w er-on reset occurred (m ust be set in softw are after a p o w er-on reset occurs) bit 0: unimplemented: read as '0'
1998 microchip technology inc. preliminary ds40181b -page 21 pic12ce67x 4.2.2.7 osccal register the oscillator calibr ation (osccal) register is used to calibr ate the inter nal 4 mhz oscillator . it contains six bits f or calibr ation . increasing the cal v alue increases the frequency . figure 4-9: osccal regi ster (ad dress 8f h ) r/w - 1 r/w - 0 r/w - 0 r/w - 0 r/w -0 r/w -0 u- 0 u-0 cal 5 cal 4 cal 3 cal 2 cal 1 cal 0 r = readab le bit w = wr itab le bit u = unimplemented bit, re ad as ? - n = v alue at por reset bit7 bit0 bit 7-2 : cal< 5 :0>: c alibr ation bit 1-0: unimplemented, read as 0
pic12ce67x ds40181b -page 22 preliminary 1998 microchip technology inc. 4.3 pcl and pcla th the prog r am counter (pc) is 13-bits wide . the lo w b yte comes from the p cl register , which is a readab le and wr itab le register . the high b yte (pc<12:8>) is n ot directly readab le or wr itab le and comes from pcla th . on an y reset, the pc is cleared. figure 4-10 sho ws the tw o situations f or the loading of the pc . the upper e xample in the gure sho ws ho w the pc is loaded on a wr ite to pcl (pcla th<4:0> ? pch). the lo w er e xam- ple in the gure sho ws ho w the pc is loaded dur ing a call or goto instr uction (pcla th<4:3> ? pch). figure 4-10: loading of pc in diff erent situations 4.3.1 computed go t o a computed go t o is accomplished b y adding an off- set to the prog r am counter ( addwf pcl ). when doing a tab le read using a computed go t o method, care should be e x ercised if the tab le location crosses a pcl memor y boundar y (each 256 b yte b loc k). ref er to the application note ?mplementing a t ab le read" (an 556). pc 12 8 7 0 5 pcla th<4:0> pcla th instr uction with alu result goto, call opcode <10:0> 8 pc 12 11 10 0 11 pcla th<4:3> pch pcl 8 7 2 pcla th pch pcl pcl as destination 4.3.2 stac k the pic12c67x f amily has an 8 le v el deep x 13-bit wide hardw are stac k. the stac k space is not par t of either prog r am or data space and the stac k pointer is not readab le or wr itab le . the pc is pushed onto t he stac k when a call instr uction is e x ecuted or an inter- r upt causes a br anch. the stac k is pop ed in the e v ent of a return, retlw or a retfie instr uction e x ecution. pcla th is not aff ected b y a push or pop oper ation. the stac k oper ates as a circular b uff er . t his means that after the stac k has been pushed eight times , the ninth push o v erwr ites the v alue that w as stored from the rst push. t he tenth push o v erwr ites the second push (and so on). 4.4 pr ogram memor y p a ging the pic12ce67x ignores both paging bits p cla th<4:3>, which are used to access prog r am memor y when more than one page is a v ailab le . t he use of pcla th< 4: 3> as g ener al pur pose read/wr ite bits f or the pic12ce67x is not recommended since this ma y aff ect upw ard compatibility with future prod- ucts . note 1: there are no status bits to indicate stac k o v er o w or stac k under o w conditions . note 2: there are no instr uctions /m nemonics calle d push or pop . these are actions that occur from the e x ecution of the call, return, retlw, and retfie instr uc- tions , or the v ector ing to an interr upt address .
1998 microchip technology inc. preliminary ds40181b -page 23 pic12ce67x 4.5 indirect ad dressing, indf and fsr register s the indf register is not a ph ysical register . a ddressing the indf register will cause indirect addressing. indirect addressing is possib le b y using the indf reg- ister . an y instr uction using the indf register actually accesses the register p ointed to b y the file select re g- ister , f sr . reading the indf register itself indirectly (fsr = '0') will read 0 0h. wr iting to the indf register indirectly results in a no-oper ation (although status bits ma y be aff ected). an eff ectiv e 9-bit address is obtained b y concatenating the 8-bit fsr register and the irp bit (st a tus<7>), as sho wn in figure 4-11 . ho w e v er , irp is not used in the pic12ce67x . a simple prog r am to clear ram location s 20h-2fh using indirect addressing is sho wn in example 4-1 . example 4-1: indi rect ad dressing movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr,f ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next continue : ;yes continue figure 4-11: d irect/indi rect ad dressing f or register le map detail see figure 4-2 . note 1: the rp1 and irp bits are reser v ed, alw a ys maintain these bits clear . data memor y indirect ad dressing direct ad dressing bank select location select (1) rp1 rp0 6 0 from opcode irp (1) fsr register 7 0 bank select location select 00 01 10 11 180 h 1ffh 00 h 7f h bank 0 bank 1 bank 2 bank 3 not used
pic12ce67x ds40181b -page 24 preliminary 1998 microchip technology inc. no tes:
1998 microchip technology inc. preliminary ds40181b -page 25 pic12ce67x 5.0 i/o p or t as with an y other register , the i/o register can be wr itten and read under prog r am control. ho w e v er , read instr uctions (e .g., movf gpio,w ) alw a ys read the i/o pins independent of the pin s input/output modes . on reset , all i/o por ts are de ned as input (inputs are at hi-impedance) since the i/o control registers are all set. 5.1 gpio gpio is an 8-bit i/o register . only the lo w order 6 bits are used (gp5:gp0). bits 6 and 7 (sd a and scl) are used b y the eepr om per ipher al. ref er to section 6.0 and appendix a f or use of sd a and scl . please note that gp3 is an input only pin. the con gur ation w ord can set se v er al i/o s to alter nate functions . when acting as alter nate functions the pins will read as ? dur ing por t read. pins gp0, gp1, and gp3 can be con gured with w eak pull-ups and also with interr upt o n change . the interr upt on change and w eak pull-up functions are not pin selectab le . if pin 4 is con gured as mclr , the w eak pull-up is alw a ys on . interr upt o n change f or this pin is not set and gp3 will read as '0'. interr upt on change is enab led b y setting intcon<3>. note that e xter nal oscillator use o v err ides the gpio functions on gp4 and gp5. 5.2 tris register th is register controls the data direction f or gpio . a '1' from a tris register bit puts the corresponding output dr iv er in a hi-impedance mode . a '0' puts the contents of the output data latch on the selected pins , enab ling the output b uff er . the e xceptions are gp3 which is input only and its tris bit will alw a ys read as '1' . upon reset, th e tris register is all '1's , making all pins inputs . tris f or pins gp4 and gp5 is f orced to a 1 where appropr iate . wr ites to tris <5:4> will ha v e an eff ect in extrc and intrc oscillator modes only . when gp4 is con gured as clk out , changes to tris<4> will ha v e no eff ect. 5.3 i/o interfacing the equiv alent circuit f or an i/o por t pin is sho wn in figure 5-2. all por t pins , e xcept gp3 which is input only , ma y be used f or both input and output oper ations . f or input oper ations these por ts are non- latching. an y input m ust be present until read b y an input instr uction (e .g., movf gpio,w ). the outputs are latched and remain unchanged until the output latch is note: a read of the por ts reads the pins , not the output data latches . that is , if an output dr iv er on a pin is enab led and dr iv en high, b ut the e xter nal system is holding it lo w , a read of the por t will indicate that the pin is lo w . re wr itten. t o use a por t pin as output, the corresponding direction control bit in tris m ust be cleared (= 0). f or use as an input, the corresponding tris bit m ust be set. an y i/o pin (e xcept gp3) can be prog r ammed individually as input or output . p or t pins gp6 and gp7 are used f or the ser ial eepr om interf ace . these por t pins are not a v ailab le e xter nally on the pac kage . users should a v oid wr iting to pins gp6 and gp7 when not comm unicating with the ser ial eepr om memor y . please see section 6.0, eepr om p er ipher al oper ation, f or inf or mation on ser ial eepr om comm unication. figure 5-1: equiv alent cir cuit f or a single i/o pin note: on a p o w er-on reset, gp0, gp1, gp2, gp4 a re con gured as analog inputs and read as '0'. note 1: i/o pins ha v e protection diodes to v dd and v ss . data bu s q d q ck q d q ck p n wr p or t tris ? data tris rd p or t v ss v dd i/o p in (1) w r eg l atch l atch reset gp3 is input only with no data latch and no output dr iv ers .
pic12ce67x ds40181b -page 26 preliminary 1998 microchip technology inc. t ab le 5-1: summar y of p or t register s ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on p o wer -on reset v alue on all other resets 85h tris gpio data direction register --11 1111 --11 1111 8 1 h option gppu intedg t0cs t0se psa ps2 ps1 ps0 11 11 1111 11 11 1111 0 3 h st a tus irp (1) rp1 (1) rp0 t o pd z dc c 0001 1xxx 000q quuu 0 5h gpio scl sd a gp5 gp4 gp3 gp2 gp1 gp0 11xx xxxx 11uu uuuu legend: shaded cells not used b y p or t registers , read as ?? ?= unimplemented, read as '0', x = unkno wn, u = unchanged, q = see tab les in section 9.4 f or possib le v alues . note 1: the irp and rp1 bits are reser v ed on the pic12ce67x, alw a ys maintain these bits clear . 5.4 i /o pr ogramming considerations 5.4.1 bi-directional i/o p or ts an y instr uction which wr ites , oper ates inter nally as a read f ollo w ed b y a wr ite oper ation. the bcf and bsf instr uctions , f or e xample , read the register into the cpu , e x ecute the bit oper ation and wr ite the result bac k to the register . caution m ust be used when these instr uctions are applied to a por t with both inputs and outputs de ned. f or e xample , a bsf oper ation on bit5 of gpio w ill cause all eight bits of gpio t o be read into the cpu . then the bsf oper ation tak es place on bit5 and gpio i s wr itten to the output latches . if another bit of gpio i s used as a bi-directional i/o pin (e .g., bit0) and it is de ned as an input at this time , the input signal present on the pin itself w ould be read into the cpu and re wr itten to the data latch of this par ticular pin, o v erwr iting the pre vious content. as long as the pin sta ys in the input mode , no prob lem occurs . ho w e v er , if bit0 is s witched to an output, the content of the data latch ma y no w be unkno wn. reading the por t register , reads the v alues of the por t pins . wr iting to the por t register wr ites the v alue to the por t latch. when using read-modify-wr ite instr uctions (e x. bcf, bsf , etc.) on a por t, the v alue of the por t pins is read, the desired oper ation is done to this v alue , and this v alue is then wr itten to the por t latch. example 5-1 sho ws the eff ect of tw o sequential read- modify-wr ite instr uctions on an i/o por t . example 5-1: read- modify-write instructions on an i/o p or t ;initial gpio settings ; gpio<5:3> inputs ; gpio<2:0> outputs ; ; gpio latch gpio pins ; ---------- ---------- bcf gpio, 5 ;--01 -ppp --11 pppp bcf gpio, 4 ;--10 -ppp --11 pppp movlw 007h ; tris gpio ;--10 -ppp --11 pppp ; ;note that the user may have expected the pin ;values to be --00 pppp. the 2nd bcf caused ;gp5 to be latched as the pin value (high). a pin activ ely outputting a lo w or high should not be dr iv en from e xter nal de vices at the same time in order to change the le v el on this pin (?ired-or? ?ired-and?. the resulting high output currents ma y damage the chip . figure 5-2: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instr uction f etched gp5:gp0 mo vwf gpio nop p or t pin sampled here nop mo vf gpio ,w instr uction e x ecuted mo vwf gpio (wr ite to gpio) nop mo vf gpio ,w this e xample sho ws a wr ite to gpio f ollo w ed b y a read from gpio . data setup time = (0.25 t cy ? t pd ) where: t cy = instr uction cycle . t pd = propagation dela y theref ore , at higher cloc k frequencies , a wr ite f ollo w ed b y a read ma y be prob lematic. (read gpio) p or t pin wr itten h ere
1998 microchip technology inc. preliminary ds40181b -page 27 pic12ce67x 6.0 eepr om p eripheral operatio n the pic12ce673 and pic12ce674 each ha v e 16 b ytes of eepr om data memor y . the eepr om mem- or y has an endur ance of 1,000,000 er ase/wr ite cycles and a data retention of g reater than 40 y ears . the eepr om data memor y suppor ts a bi-directional 2-wire b us and data tr ansmission protocol. these tw o-wires are ser ial data (sd a) and ser ial cloc k (scl), that are mapped to bit6 and bit7, respectiv ely , of the gpio reg- ister (sfr 06h). unlik e the gp0-gp5 that are con- nected to the i/o pins , sd a and scl are only connected to the inter nal eepr om per ipher al. f or most applications , all that is required is calls to the f ol- lo wing functions: ; byte_write: byte write routine ; inputs: eeprom address eeaddr ; eeprom data eedata ; outputs: return 01 in w if ok, else return 00 in w ; ; read_current: read eeprom at address currently held by ee device. ; inputs: none ; outputs: eeprom data eedata ; return 01 in w if ok, else return 00 in w ; ; read_random: read eeprom byte at supplied address ; inputs: eeprom address eeaddr ; outputs: eeprom data eedata ; return 01 in w if ok, else return 00 in w the code f or these functions is a v ailab le on our w eb site (www .microchip .com) . the code will be accessed b y either including the source code fl 6 7x i nc .asm or b y linking flash67x.asm. flash62.imc pro vides e xter nal de nition to the calling prog r am. 6.0.1 ser ial data sd a i s a bi-directional pin used to tr ansf er addresses and data into and data out of the de vice . f or nor mal data tr ansf er sd a is allo w ed to change only dur ing scl lo w . changes dur ing scl high are reser v ed f or indicating the st ar t and st op condi- tions . 6.0.2 ser ial cloc k this scl input is used to synchroniz e the data tr ansf er from and to the eepr om . 6.1 b us chara cteristics the f ollo wing b us pr otocol is to be used with the eepr om data memor y . in this section, the ter m ?ro- cessor is used to denote the por tion of the pic12ce67x that interf aces to the eepr om via soft- w are . data tr ansf er ma y be initiated only when the b us is not b usy . dur ing data tr ansf er , the data line m ust remain stab le whene v er the cloc k line is high. changes in the data line while the cloc k line is high will be inter preted as a st ar t or st op condition. accordingly , the f ollo wing b us conditions ha v e been de ned ( figure 6-1 ). 6.1.1 bus not busy (a) both data and cloc k lines remain high. 6.1.2 star t data t r ansf er (b) a high to lo w tr ansition of the sd a line while the cloc k (scl) is high deter mines a st ar t condition. all commands m ust be preceded b y a st ar t condition. 6.1.3 stop data t r ansf er (c) a lo w to high tr ansition of the sd a line while the cloc k (scl) is high deter mines a st op condition. all oper ations m ust be ended with a st op condition. 6.1.4 data v alid (d) the state of the data line represents v alid data when, after a st ar t condition, the data line is stab le f or the dur ation of the high per iod of the cloc k signal. the data on the line m ust be changed dur ing the lo w per iod of the cloc k signal. there is one bit of data per cloc k pulse . each data tr ansf er is initiated with a st ar t condition and ter minated with a st op condition. the n umber of the data b ytes tr ansf erred betw een the st ar t and st op conditions is deter mined b y the processor de vice and is theoretically unlimited. 6.1.5 ac kno wledge the eepr om , when addressed, will gener ate an ac kno wledge after the reception of each b yte . the pro- cessor m ust gener ate an e xtr a cloc k pulse which is associated with this ac kno wledge bit. the de vice that ac kno wledges has to pull do wn the sd a line dur ing the ac kno wledge cloc k pulse in such a w a y that the sd a line is stab le lo w dur ing the high per iod of the ac kno wledge related cloc k pulse . of course , setup and hold times m ust be tak en into account. the processor m ust signal an end of data to the eepr om b y not gener ating an ac kno wledge bit on the last b yte that has been cloc k ed out of the eepr om . in this case , the eepr om m ust lea v e the data line high to enab le the processor to gener ate the st op condition ( figure 6-2 ). note: ac kno wledge bits are not gener ated if an inter nal prog r amming cycle is in prog ress .
pic12ce67x ds40181b -page 28 preliminary 1998 microchip technology inc. figure 6-1: d a t a transfer seq uence on the serial b us figure 6-2: ac kno wledg e timing (a) (b) (c) (d) (a) (c) scl sd a st ar t condition address or a ckno wledge v alid d a t a allo wed t o change st op condition scl 9 8 7 6 5 4 3 2 1 1 2 3 t r ansmitter m ust release the sd a line at this point allo wing the receiv er to pull the sd a line lo w to ac kno wledge the pre vious eight bits of data. receiv er m ust release the sd a line at this point so the t r ansmitter can contin ue sending data. data from tr ansmitter data from tr ansmitter sd a ac kno wledge bit 6.2 de vice ad dressing after gener ating a st ar t condition, the processor tr ansmits a control b yte consisting of a eepr om address and a read/ wr ite bit that indicates what type of oper ation is to be perf or med. the eepr om address consists of a 4-bit de vice code (1010) f ollo w ed b y three don't care bits . the last bit of the control b yte deter mines the oper ation to be perf or med. when set to a one a read oper ation is selected, and when set to a z ero a wr ite oper ation is selected. ( figure 6-3 ). the b us is monitored f or its cor- responding eepr om address all the time . it gener ates an ac kno wledge bit if the eepr om address w as tr ue and it is not in a prog r amming mode . figure 6-3: contr ol byte f ormat 1 0 1 0 x x x s a ck r/ w de vice select bits don? care bits eepr om address ac kno wledge bit star t bit read/ wr ite bit
1998 microchip technology inc. preliminary ds40181b -page 29 pic12ce67x 6.3 write opera tions 6.3.1 byte wr ite f ollo wing the star t signal from the processor , the de vice code (4 bits), the don't care bits (3 bits), and the r/ w bit (which is a logic lo w) are placed onto the b us b y the processor . this indicates to the addressed eepr om that a b yte with a w ord address will f ollo w after it has gener ated an ac kno wledge bit dur ing the ninth cloc k cycle . theref ore , the ne xt b yte tr ansmitted b y the processor is the w ord address and will be wr itten into the address pointer . only the lo w er f our address bits are used b y the de vice , and the upper f our bits are don? cares . the address b yte is ac kno wledgeab le and the processor will then tr ansmit the data w ord to be wr itten into the addressed memor y location. the mem- or y ac kno wledges again and the processor gener ates a stop condition. this initiates the inter nal wr ite cycle , and dur ing this time will not gener ate ac kno wledge sig- nals ( figure 6-5 ). after a b yte wr ite command, the inter- nal address counter will not be incremented and will point to the same address location that w as just wr itten. if a stop bit is tr ansmitted to the de vice at an y point in the wr ite command sequence bef ore the entire sequence is complete , then the command will abor t and no data will be wr itten. if more than 8 data bits are tr ansmitted bef ore the stop bit is sent, then the de vice will clear the pre viously loaded b yte and begin loading the data b uff er again. if more than one data b yte is tr ansmitted to the de vice and a stop bit is sent bef ore a full eight data bits ha v e been tr ansmitted, then the wr ite command will abor t and no data will be wr itten. the eepr om memor y emplo ys a v cc threshold detector circuit which disab les the inter nal er ase/wr ite logic if the v cc is belo w minim um v dd . byte wr ite oper ations m ust be preceded and immediately f ollo w ed b y a b us not b usy b us cycle where both sd a and scl are held high. 6.4 a ckno wledge polling since the eepr om will not ac kno wledge dur ing a wr ite cycle , this can be used to deter mine when the cycle is complete (this f eature can be used to maximiz e b us throughput). once the stop condition f or a wr ite com- mand has been issued from the processor , the de vice initiates the inter nally timed wr ite cycle . a ck polling can be initiated immediately . this in v olv es the proces- sor sending a star t condition f ollo w ed b y the control b yte f or a wr ite command (r/ w = 0). if the de vice is still b usy with the wr ite cycle , then no a ck will be retur ned. if no a ck is retur ned, then the star t bit and control b yte m ust be re-sent. if the cycle is complete , then the de vice will retur n the a ck and the processor can then proceed with the ne xt read or wr ite command. see figure 6-4 f or o w diag r am. figure 6-4: a ckno wledge polling flo w send wr ite command send stop condition to initiate wr ite cycle send star t send control byte with r/w = 0 did eepr om ac kno wledge (a ck = 0)? ne xt oper ation no yes figure 6-5: byte write s p b us a ctivity pr ocessor sd a line b us a ctivity s t a r t s t o p contr ol byte w ord address d a t a a c k a c k a c k 1 0 x 1 0 x x x x = don? care bit x x x 0
pic12ce67x ds40181b -page 30 preliminary 1998 microchip technology inc. 6.5 read opera tions read oper ations are initiated in the same w a y as wr ite oper ations with the e xception that the r/ w bit of the eepr om address is set to one . there are three basic types of read oper ations: current address read, r andom read, and sequential read. 6.5.1 current address read it contains an address counter that maintains the address of the last w ord accessed, inter nally incre- mented b y one . theref ore , if the pre vious read access w as to address n, the ne xt current address read oper a- tion w ould access data from address n + 1. upon receipt of the eepr om address with the r/ w bit set to one , the eepr om issues an ac kno wledge and tr ans- mits the eight bit data w ord. the processor will not ac kno wledge the tr ansf er b ut does gener ate a stop condition and the eepr om discontin ues tr ansmission ( figure 6-6 ). 6.5.2 random read random read oper ations allo w the processor to access an y memor y location in a r andom manner . t o perf or m this type of read oper ation, rst the w ord address m ust be set. this is done b y sending the w ord address to the eepr om as par t of a wr ite oper ation. after the w ord address is sent, the processor gener ates a star t condi- tion f ollo wing the ac kno wledge . this ter minates the wr ite oper ation, b ut not bef ore the inter nal address pointer is set. then the processor issues the control b yte again b ut with the r/ w bit set to a one . it will then issue an ac kno wledge and tr ansmits the eight bit data w ord. the processor will not ac kno wledge the tr ansf er b ut does gener ate a stop condition and the eepr om discontin ues tr ansmission ( figure 6-7 ). after this com- mand, the inter nal address counter will point to the address location f ollo wing the one that w as just read. 6.5.3 sequential read sequential reads are initiated in the same w a y as a r an- dom read e xcept that after the de vice tr ansmits the rst data b yte , the processor issues an ac kno wledge as opposed to a stop condition in a r andom read. this directs the eepr om to tr ansmit the ne xt sequentially addressed 8-bit w ord ( figure 6-8 ). t o pro vide sequential reads , it contains an inter nal address pointer which is incremented b y one at the completion of each read oper ation. this address pointer allo ws the entire memor y contents to be ser ially read dur ing one oper ation. figure 6-6: current address read figure 6-7: random read figure 6-8: seq uential read b us a ctivity pr ocessor sd a line b us a ctivity p s s t o p contr ol byte s t a r t d a t a a c k n o a c k 1 1 0 0 x x x 1 x = don? care bit p b us a ctivity pr ocessor sd a line b us a ctivity s t a r t s t o p contr ol byte a c k w ord address (n) contr ol byte s t a r t d a t a (n) a c k a c k n o a c k x x x x s 1 1 0 0 x x x 0 s 1 1 0 0 x x x 1 x = don? care bit p b us a ctivity pr ocessor sd a line b us a ctivity s t o p contr ol byte a c k n o a c k d a t a n d a t a n + 1 d a t a n + 2 d a t a n + x a c k a c k a c k
1998 microchip technology inc. preliminary ds40181b -page 31 pic12ce67x 7.0 timer0 module the timer0 module timer/counter has the f ollo wing f ea- tures: 8-bit timer/counter readab le and wr itab le 8-bit softw are prog r ammab le prescaler inter nal or e xter nal cloc k select interr upt on o v er o w from ffh to 00h edge select f or e xter nal cloc k figure 7-1 is a simpli ed b loc k diag r am of the timer0 module . timer mode is selected b y clear ing bit t0cs (option<5>). in timer mode , the timer0 module will increment e v er y instr uction cycle (without prescaler). if the tmr0 register is wr itten, the increment is inhibited f or the f ollo wing tw o instr uction c ycles ( figure 7-2 and figure 7-3 ). the user can w or k around this b y wr iting an adjusted v alue to the tmr0 register . counter mode is selected b y setting bit t0cs (option<5>). in counter mode , timer0 will increment either on e v er y r ising or f alling edge of pin ra4/t0cki. the incrementing edge is deter mined b y the timer0 source edge select bit t0se (option<4>). clear ing bit t0se s elects the r ising edge . restr ictions on the e xter nal cloc k input are d iscussed in detail in section 7.2 . the prescaler is m utually e xclusiv ely shared betw een the timer0 module and the w atchdog timer . the pres- caler assignment is controlled in softw are b y control bit psa (option<3>). clear ing bit psa will assign the prescaler to the timer0 module . the prescaler is not readab le or wr itab le . when the prescaler is assigned to the timer0 module , prescale v alue s of 1:2, 1:4, . .., 1:256 are selectab le . section 7.3 details the oper ation of the prescaler . 7.1 timer0 in terrupt the tmr0 i nterr upt is gener ated when the tmr0 reg- ister o v er o ws from ffh to 00h. this o v er o w sets bit t0if (intcon<2>). the interr upt can be mask ed b y clear ing bit t0ie (intcon<5>). bit t0if m ust be cleared in softw are b y the timer0 module interr upt ser- vice routine bef ore re-enab ling this interr upt. the tmr0 i nterr upt cannot a w ak en the processor from sleep since the timer is shut off dur ing sleep . see figure 7- 4 f or timer0 interr upt timing. figure 7-1: timer0 blo c k dia gram figure 7-2: timer0 timing: in ternal cloc k/no prescale note 1: t0cs , t0se, psa, ps2:ps0 (option<5:0>). 2: the prescaler is shared with w atchdog timer (ref er to figure 7-6 f or detailed b loc k diag r am) . gp2/t0cki / t0se 0 1 1 0 an2 /int t0cs f osc /4 prog r ammab le prescaler sync with inter nal cloc ks tmr0 psout (2 t cy d ela y) psout data b us 8 psa ps2, ps1, ps0 set interr upt ag bit t0if on o v er o w 3 pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (prog r am counter) instr uction f etch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 t0 mo vwf tmr0 mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w wr ite tmr0 e x ecuted read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instr uction ex ecuted
pic12ce67x ds40181b -page 32 preliminary 1998 microchip technology inc. figure 7-3: timer0 timing: internal cloc k/prescale 1:2 figure 7-4: timer0 inter rupt timing pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (prog r am counter) instr uction f etch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 mo vwf tmr0 mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w wr ite tmr0 e x ecuted read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instr uction ex ecute q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 1 1 osc1 clk out (3) timer0 t0if bit (intcon<2>) feh gie bit (intcon<7>) instr uction pc instr uction f etched pc pc +1 pc +1 0004h 0005h instr uction e x ecuted inst (pc) inst (pc-1) inst (pc+1) inst (pc) inst (0004h) inst (0005h) inst (0004h) dumm y cycle dumm y cycle ffh 00h 01h 02h note 1: interr upt ag bit t0if i s sampled here (e v er y q1). 2: interr upt latency = 3t cy where tcy = instr uction cycle time . 3: clk out is a v ailab le only in rc oscillator mode . f lo w
1998 microchip technology inc. preliminary ds40181b -page 33 pic12ce67x 7.2 using timer0 with an external cloc k when an e xter nal cloc k input is used f or timer0, it m ust meet cer tain requirements . the requirements ensure the e xter nal cloc k can be synchroniz ed with the inter nal phase cloc k (t osc ). also , there is a dela y in the actual incrementing of timer0 after synchronization. 7.2.1 exter nal cloc k synchronization when no prescaler is used, the e xter nal cloc k input is the same as the prescaler output. the synchronization of t0cki with the inter nal ph ase cloc ks is accom- plished b y sampling the prescaler output on the q2 and q4 cycles of the inter nal phase cloc ks ( figure 7-5 ). theref ore , it is necessar y f or t0cki to be high f or at least 2 t osc (and a small rc dela y of 20 ns) and lo w f or at least 2 t osc (and a small rc dela y of 20 ns). ref er to the electr ical speci cation of the desired de vice . when a prescaler is used, the e xter nal cloc k input is divided b y the asynchronous r ipple-counter type pres- caler so that the prescaler output is symmetr ical. f or the e xter nal cloc k to meet the sampling requirement, the r ipple-counter m ust be tak en into account. there- f ore , it is necessar y f or t0cki to ha v e a per iod of at least 4 t osc (and a small rc dela y of 40 ns) divided b y the prescaler v alue . the only requirement on t0cki high and lo w time is that the y do not violate the mini- m um pulse width requirement of 10 ns . ref er to par am- eters 40, 41 and 42 in the electr ical speci cation of the desired de vice . 7.2.2 tmr0 increment dela y since the prescaler output is synchroniz ed with the inter nal cloc ks , there is a small dela y from the time the e xter nal cloc k edge occurs to the time the timer0 mod- ule is actually incremented. figure 7-5 sho ws the dela y from the e xter nal cloc k edge to the timer incrementing. figure 7-5: timer0 timing with e xternal cloc k q 1 q 2 q 3 q4 q 1 q 2 q 3 q4 q 1 q 2 q 3 q4 q 1 q 2 q 3 q4 exter nal cloc k input or prescaler output (2) exter nal cloc k/prescaler output after sampling increment timer0 (q4) timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling note 1: dela y from cloc k input change to timer0 increment is 3 t osc to 7 t osc. (dur ation of q = t osc). theref ore , the error in measur ing the inter v al betw een t w o edges on timer0 input = 4 t osc max. 2: exter nal cloc k if no prescaler selected, prescaler output otherwise . 3: the arro ws indicate the points in time where sampling occurs . (3) (1)
pic12ce67x ds40181b -page 34 preliminary 1998 microchip technology inc. 7.3 p re scaler an 8-bit counter is a v ailab le as a prescaler f or the timer0 module , or as a post s caler f or the w atchdog timer , respectiv ely ( figure 7-6 ). f or simplicity , this counter is being ref erred to as ?rescaler throughout this data sheet. note that there is only one prescaler a v ailab le which is m utually e xclusiv e ly shared betw een the timer0 module and the w atchdog timer . thus , a prescaler assignment f or the timer0 module means that there is no prescaler f or the w atchdog timer , and vice-v ersa. the psa and ps2 :p s0 bits (option<3:0>) deter mine the prescaler assignment and prescale r atio . when assigned to the timer0 module , all instr uctions wr iting to the tmr0 register (e .g. clrf 1, movwf 1, bsf 1,x . ...etc.) will clear the prescaler . when assigned to wdt , a clrwdt instr uction will clear the prescaler along with the w atchdog timer . the prescaler is not readab le or wr itab le . figure 7-6: bloc k dia gra m of the timer0 / wdt prescaler gp2 / t0cki/ t0se an2 /int m u x clk out (=f osc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x w atchdog timer psa 0 1 0 1 wdt time-out ps 2:p s 0 8 note: t0 cs , t0 se, psa, ps 2:p s 0 a re (o ption <5:0>). psa wdt enab le bit m u x 0 1 0 1 data bus set ag bit t0if on ov er o w 8 psa t0cs
1998 microchip technology inc. preliminary ds40181b -page 35 pic12ce67x 7.3.1 switching pre scaler assignment the prescaler assignment is fully under softw are con- trol, i.e ., it can be changed ?n the y dur ing prog r am e x ecution. example 7-1: changin g prescaler ( timer0 ? wdt ) bcf status, rp0 ;bank 0 clrf tmr0 ;clear tmr0 & prescaler bsf status, rp0 ;bank 1 clrwdt ;clears wdt movlw b 'xxxx1xxx' ; select new prescale movwf option _reg ;value & wdt bcf status, rp0 ;bank 0 note: t o a v oid an unintended de vice reset , the f ollo wing instr uction sequence (sho wn in example 7-1 ) m ust be e x ecuted when changing the prescaler assignment from timer0 to the wdt . this sequence m ust be f ollo w ed e v en if the wdt is disab led. t o change prescaler from the wdt to the timer0 mod- ule use the sequence sho wn in example 7-2 . example 7-2: cha nging prescaler (wdt ? timer0) clrwdt ;clear wdt and ;prescaler bsf status, rp0 ;bank 1 movlw b 'xxxx0xxx' ; select tmr0, new ;prescale value and movwf option _reg ;clock source bcf status, rp0 ;bank 0 t ab le 7-1: register s associated with timer0 ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on por v alue on all other resets 01h tmr0 timer0 module s register xxxx xxxx uuuu uuuu 0bh/8bh intcon gie pe ie t0ie inte gpi e t0if intf gpi f 0000 000x 0000 000u 81h option gppu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h tris tris5 tris4 tris3 tris2 tris1 tris0 -- 11 1111 -- 11 1111 legend: x = unkno wn, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used b y timer0.
pic12ce67x ds40181b -page 36 preliminary 1998 microchip technology inc. no tes:
1998 microchip technology inc. preliminary ds40181b -page 37 pic12ce67x figure 8-1: a dcon0 register (ad dress 1f h ) r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 adcs1 adcs0 r chs1 chs0 go/ done r adon r = readab le bit w = wr itab le bit u = unimplemented bit, re ad as ? - n = v alue at por reset bit7 bit0 bit 7-6: adcs1:adcs0: a/d con v ersion cloc k sele ct bits 00 = f osc /2 01 = f osc /8 10 = f osc /32 11 = f rc (cloc k der iv ed from an rc oscillation) bit 5: reser ved bit 4-3: ch s1:chs0: analog channel select bits 0 0 = channel 0, (gp0/an0) 0 1 = channel 1, (gp1/an1) 1 0 = channel 2, (gp2/an2) 1 1 = channel 3, (gp4/an3) bit 2: go/ done : a/d con v ersion status bit if adon = 1 1 = a/d con v e rsion in prog ress (setting this bit star ts the a/d con v ersion) 0 = a/d con v ersion not in prog ress (this bit is automatically cleared b y hardw are when the a/d con v er- sion is complete) bit 1: reser ved bit 0: adon: a/d on bit 1 = a/d con v er ter module is oper ating 0 = a/d con v er ter module is shutoff and consumes no oper ating current 8.0 analog - to - digital con ver ter (a/d ) module the analog-to-digital (a /d ) con v er ter module has f our analog inputs . the a /d a llo ws con v ersion of an analog input signal to a corresponding 8-bit digital n umber (ref er to applica- tion note a n546 f or use of a/d con v er ter). the output of the sample and hold is the input into the con v er ter , which gener ates the result via successiv e appro xima- tion. the analog ref erence v oltage is softw are select- ab le to either the de vice s positiv e supply v oltage ( v dd ) or the v oltage le v el on the gp1/an1/ v ref pin. the a/d con v er ter has a unique f eature of being ab le to oper ate while the de vice is in sleep mode . the a/d module has three registers . these registers are: a/d result re gister ( adres) a/d control regi ster 0 ( adcon0) a/d control regis ter 1 (adcon1) the adcon0 register , sho wn in figure 8-1 , controls the oper ation of the a/d module . the adcon1 regis- ter , sho wn in figure 8-2 , con gures the functions of the por t pins . the por t pins can be con gured as analog inputs ( gp1 c an also be a v oltage ref erence) or as dig- ital i/o . note: if the por t pins are con gured as analog inputs (reset condition), reading the por t (mo vf g p ,w) results in reading '0's . note: changing adcon1 register can cause the gpif and intf ags to be set in the intcon register . these interr upts should be disab led pr ior to modifying adcon1.
pic12ce67x ds40181b -page 38 preliminary 1998 microchip technology inc. figure 8-2: adcon1 register ( ad dress 9f h ) u-0 u-0 u-0 u-0 u-0 r/w -0 r/w -0 r/w -0 pcfg2 pcfg1 pcfg0 r = readab le bit w = wr itab le bit u = unimplemented bit, re ad as ? - n = v alue at por reset bit7 bit0 bit 7-2: unimplemented: re ad as '0' bit 1-0: pcfg 2: pcfg0: a/d p or t con gur ation control bits a = analog input d = digital i/o note 1: v alue on reset. note 2: an y instr uction that reads a pin con gured as an analog input will read a '0'. pcfg2:pcfg0 gp4 gp2 gp1 gp0 v ref 000 (1) a a a a v dd 001 a a v ref a gp1 010 d a a a v dd 011 d a v ref a gp1 100 d d a a v dd 101 d d v ref a gp1 110 d d d a v dd 111 d d d d v dd
1998 microchip technology inc. preliminary ds40181b -page 39 pic12ce67x the adres register contains the result of the a/d con- v ersion. when the a/d con v ersion is complete , the result is loaded into the adres register , the go/ done bit (adcon0<2>) is cleared, and a /d interr upt ag bit a dif (pie1<6>) i s set. the b loc k diag r ams of the a/d module are sho wn in figure 8-3 . after the a/d module has been con gured as desired, the selected channel m ust be acquired bef ore the con- v ersion is star ted. the analog input channels m ust ha v e their corresponding tris bits selected as an input. t o deter mine sample time , see section 8.1 . after this acquisition time has elapsed the a/d con v ersion can be star ted. the f ollo wing steps should be f ollo w ed f or doing an a/d con v ersion: 1. con gu re the a/d module : con gure analog pins / v oltage ref erence / and digital i/o (adcon1 ) select a/d input channel (adcon0 ) select a/d con v ersion cloc k (adcon0 ) t ur n on a/d module (adcon0 ) 2. con gure a/d i nterr upt (if desired) : clear adif bit set adie bit set gie bit 3. w ait the required acquisition time . 4. star t con v ersion : set go/ done bit (adcon0 ) 5. w ait f or a/d con v ersion to complete , b y either : p olling f or the go/ done bit to be cleared or w aiting f or the a/d interr upt 6. read a/d result register (adres), clear bit adif if required. 7. f or ne xt con v ersion, go to step 1 or step 2 as required. the a/d con v ersion time per bit is de ned as t ad . a minim um w ait of 2 t ad is required bef ore ne xt acquisition star ts . figure 8-3: a/d bloc k dia gra m (input v oltage) v in v ref (ref erence v oltage) v dd pcfg2: pcf g0 chs1: chs 0 000 o r 010 o r 100 or 001 or gp4/an3 gp0/an0 gp2/an2 gp1/ an1/v ref 11 10 01 00 a/d con v er ter 011 or 101 110 or
pic12ce67x ds40181b -page 40 preliminary 1998 microchip technology inc. 8.1 a /d sampling requirements f or the a/d con v er ter to meet its speci ed accur acy , the charge holding capacitor ( c hold ) m ust be allo w ed to fully charge to the input channel v oltage le v el. the analog input model is sho wn in figure 8-4 . the source impedance ( r s ) and the inter nal sampling s witch ( r ss ) imped an ce directly aff ect the time required to charge the capacitor c hold . the sampling s witch ( r ss ) imped an ce v ar ies o v er the de vice v oltage ( v dd ), see figure 8-4 . the maxim um recommended imped- ance f or analog sour ces is 10 k w . after the analog input channel is selected (changed) this acquisition m ust be done bef ore the con v ersion can be s tar ted. t o calculate the minim um acquisition time , equation 8- 1 ma y be used. this equation assumes that 1/2 lsb error is used (512 steps f or the a/d). the 1/2 lsb error is the maxim um error allo w ed f or the a/d to meet its speci ed resolution. equation 8-1: a/d minim um char ging time v hold = ( v ref - ( v ref /512)) ?(1 - e (-tc/ c hold ( r ic + r ss + r s ) ) ) or tc = -(51.2 pf)(1 k w + r ss + r s ) ln(1/511) example 8-1 sho ws the calculation of the minim um required acquisition time t acq . this calculation is based on the f ollo wing system assumptions . rs = 10 k w 1/2 lsb error v dd = 5v ? rss = 7 k w t emp (system max.) = 50 c v hold = 0 @ t = 0 example 8-1: calculating the minim um required sample tim e t acq = ampli er settling time + holding capacitor cha rg ing time + t emper ature coef cient t acq = 5 m s + tc + [(t emp - 25 c)(0.05 m s/ c)] t c = - c hold ( r ic + r ss + r s ) ln(1/512) -51.2 pf (1 k w + 7 k w + 10 k w ) ln(0.0020) -51.2 pf (18 k w ) ln(0.0020) -0.921 m s (-6.2146) 5.724 m s t acq = 5 m s + 5.724 m s + [(50 c - 25 c)(0.05 m s/ c)] 10.724 m s + 1.25 m s 11.974 m s note 1: the ref erence v oltage (v ref ) has no eff ect on the equation, since it cancels itself out. note 2: the charge holding capacitor (c hold ) is not discharged after each con v ersion. note 3: the maxim um recommended impedance f or analog sources is 10 k w . this is required to meet the pin leakage speci - cation. note 4: after a c on v ersion has completed, a 2.0 t ad dela y m ust complete b ef ore acquisition can begin again. dur ing this time the holding capacitor is not con- nected to the selected a/d input channel. figure 8-4: a nalog inp ut model c pin v a rs rax 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = d a c capacitance v ss 6v sampling switch 5v 4 v 3v 2v 5 6 7 8 9 10 11 ( k w ) v dd = 51.2 pf 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold v oltage = leakage current at the pin due to = interconnect resistance = sampling s witch = sample/hold capacitance (from d a c) v ar ious junctions
1998 microchip technology inc. preliminary ds40181b -page 41 pic12ce67x 8.2 selecting the a /d con ver sion cloc k the a/d c on v ersion time per bit is de ned as t ad . the a/d con v ersion requires 9.5 t ad per 8-bit con v ersion . t he source of the a/d con v ersion cloc k is softw are selected. the f our possib le options f or t ad are: 2 t osc 8 t osc 32 t osc inter nal adc rc oscillator f or correct a/d con v ersions , the a/d con v ersion cloc k ( t ad ) m ust be selected to ensure a minim um t ad time of 1.6 m s . t ab le 8-1 sho ws the resultant t ad times der iv ed from the de vice oper ating frequencies and the a/d cloc k source selected. 8.3 conf iguring analog p or t pins the a dcon1 and tris r egisters control the oper ation of the a/d por t pins . the por t pins that are desired as analog inputs m ust ha v e their corresponding tris bit s set (input). if the tris bit is cleared (output), the digital output le v el ( v oh or v ol ) will be c on v er ted. the a/d oper ation is independent of the state of the chs 2 : chs0 b its and the tris bits . note 1: when reading the por t register , all pins con gured as analog input channel will read as cleared (a lo w le v el). pins con g- ured as digital inputs , will con v er t an ana- log input. analog le v els on a digitally con gured input will not aff ect the con v er- sion accur acy . note 2: analog le v els on an y pin that is de ned as a digital input (including the an3:an0 pins), ma y cause the input b uff er to con- sume current that is out of the de vices speci cation. t ab le 8-1: t ad vs . de vice operating frequencies ad cloc k sour ce ( t ad ) de vice frequenc y operation adcs1:adcs0 4 mhz 1.25 mhz 333.33 kh z 2 t osc 00 500 ns (2) 1.6 m s 6 m s 8 t osc 01 2.0 m s 6.4 m s 24 m s (3) 32 t osc 10 8.0 m s 25.6 m s (3) 96 m s (3) inter nal adc rc o scillator (5) 11 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1) note 1: the rc source has a typical t ad time of 4 m s . 2: these v alues violate the minim um required t ad time . 3: f or f aster con v ersion times , the selection of another cloc k source is recommended. 4: while in rc mode , with de vice frequency abo v e 1 mhz, con v ersion accur acy is out of speci cation. 5: f or e xtended v oltage de vices (lc), please ref er to electr ical speci cations section.
pic12ce67x ds40181b -page 42 preliminary 1998 microchip technology inc. 8.4 a /d con ver sions example 8-2 sho w ho w to perf or m an a/d con v ersion. the gp p ins are con gured as analog inputs . the ana- log ref erence ( v ref ) is the de vice v dd . t he a/d inter- r upt is enab led, and the a/d con v ersion cloc k is f r c . the con v ersion is perf or med on the gp0 channel. note: the go/ done bit should no t be set in the same instr uction that tur ns on the a/d . clear ing the go/ done bit dur ing a con v ersion will abor t the current con v ersion. the adres register will no t be updated with the par tially completed a/d con- v ersion sample . that is , the adres register will con- tin ue to contain the v alue of the last completed con v ersion (or the last v alue wr itten to the adres reg- ister). after the a/d con v ersion is abor ted, a 2 t ad w ait is required bef ore the ne xt acquisition is star ted. after this 2 t ad w ait, an acquisition is automatically star ted on the selected channel. example 8-2: doing an a/d con ver sion bsf status, rp0 ; select page 1 clrf adcon1 ; configure a/d inputs bsf pie1, adie ; enable a/d interrupts bcf status, rp0 ; select page 0 movlw 0xc1 ; rc clock, a/d is on, channel 0 is selected movwf adcon0 ; bcf pir1, adif ; clear a/d interrupt flag bit bsf intcon, peie ; enable peripheral interrupts bsf intcon, gie ; enable all interrupts ; ; ensure that the required sampling time for the selected input channel has elapsed. ; then the conversion may be started. ; bsf adcon0, go ; start a/d conversion : ; the adif bit will be set and the go/done bit : ; is cleared upon completion of the a/d conversion.
1998 microchip technology inc. preliminary ds40181b -page 43 pic12ce67x 8.5 a/d operation during sleep the a/d module can oper ate dur ing sleep mode . this requires that the a/d cloc k source be set to rc (adcs 1 : adcs 0 = 11 ) . when the rc cloc k source is selected , the a/d module w aits one instr uction cycle bef ore star ting the con v ersion. this allo ws the sleep instr uction to be e x ecuted, which eliminates all digital s witching noise from the con v ersion. when the con v er- sion is completed the go/ done bit will be cleared, and the result loaded into the adres register . if the a/d interr upt is enab led, the de vice will w ak e-up from sleep . if the a/d interr upt is not enab led, the a/d mod- ule will then be tur ned off , although the adon bit will remain set. when the a/d cloc k source is another cloc k option (not rc), a sleep instr uction will cause the present con v er- sion to be abor ted and the a/d module to be tur ned off , though the adon bit will remain set. t ur ning off the a/d places the a/d module in its lo w est current consumption state . 8.6 a/d accurac y/err or the o v er all accur acy of the a/d is less than 1 lsb f or v dd = 5 v 10% and the analog v ref = v dd . this o v er- all accur acy includes offset error , full scale error , and integ r al error . the a/d con v er ter is guar a nteed to be monotonic. the resolution and accur acy ma y be less when either the analog ref erence ( v dd ) is less th an 5.0v or when the analog ref erence ( v ref ) is less th an v dd . the maxim um pin leakage current is 5 m a. in systems where the de vice frequency is lo w , use of the a/d rc cloc k is p ref erred. at moder ate to high fre- quencies , t ad should be der iv ed from the de vice oscil- lator . t ad m ust not violate the minim um and should be 8 m s f or pref erred oper ation. this is because t ad , when der iv ed from t osc , is k ept a w a y from on-chip phase cloc k tr ansitions . this reduces , to a large e xtent, the eff ects of digital s witching noise . this is not possib le with the rc der iv ed cloc k. the loss of accur acy due to digital s witching noise can be signi cant if man y i/o pins are activ e . in systems where the de vice will enter sleep mode after the star t of the a/d con v ersion, the rc cloc k source selection is required. in this mode , the digital noise from the modules in sleep are stopped. this method giv es h igh a ccur acy . note: f or the a/d module to oper ate in sleep , the a/d cloc k source m ust be set to rc (adcs 1 : adcs0 = 11 ) . t o perf or m an a/d con v ersion in sleep , the go/ done bit m ust be set, f ollo w ed b y the sleep instr uc- tion. 8.7 eff ect s of a reset a de vice reset f orces all register s to their reset state . this f orces the a/d module to be tur ned off , and an y con v ersion is abor ted. the v alue that is in the adres register is not modi ed f or a r eset. the adres regis- ter will contain unkno wn data after a p o w er-on res et. 8.8 connection considerations if the input v oltage e xceeds the r ail v alues ( v ss or v dd ) b y g reater than 0.2v , then the accur acy of the con v er- sion is out of speci cation. an e xter nal rc lter is sometimes added f or anti-alias- ing of the input signal. the r component should be selected to ensure that the total source impedance is k ept under the 10 k w recommended speci cation. an y e xter nal components connected (via hi -i mpedance) to an analog input pin (capacitor , z ener diode , etc.) should ha v e v er y little leakage current at the pin. 8.9 t ransf er function the ideal tr ansf er function of the a/d con v er ter is as f ol- lo ws: the f irst tr ansition occurs when the analog input v oltage ( v ain ) is 1 lsb (or analog v ref / 256) ( figure 8-5 ) . figure 8-5: a/d t ransf er function note: f or the pic 12c e 67x, c are m ust be tak en when using the gp4 pin in a/d con v er- sions due to its pro ximity to the osc1 pin. digital code output ffh feh 04h 03h 02h 01h 00h 0.5 lsb 1 lsb 2 lsb 3 lsb 4 lsb 255 lsb 256 lsb (full scale) analog input v oltage
pic12ce67x ds40181b -page 44 preliminary 1998 microchip technology inc. figure 8-6: flo wc ha r t of a/d operation t ab le 8-2: summar y of a/d register s ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on p o wer -o n r eset v alue o n all other r esets (1) 0bh/8bh intcon gie peie t0ie inte gpi e t0if intf gpi f 0000 000x 0000 000u 0ch pir1 adif -0-- ---- -0-- ---- 8ch pie1 adie -0-- ---- -0-- ---- 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 r chs1 chs0 go/ done r adon 0000 00 00 0000 00 00 9fh adcon1 pcfg2 pcfg1 pcfg0 -- -- -00 0 -- -- -00 0 05h gpio gp5 gp4 gp3 gp2 gp1 gp0 -- xx xxxx -- uu uuuu 85h tris tris 5 tris4 tris3 tris2 tris1 tris0 -- 11 1111 -- 11 1111 legend: x = unkno wn, u = unchanged, - = unimplemented read as '0', r = reser v ed. shaded cells are not used f or a/d con v ersion. note 1: these registers can be addressed from either bank. acquire adon = 0 adon = 0? go = 0? a/d cloc k go = 0 adif = 0 abor t con v ersion sleep p o w er -d o wn a/d w ait 2 t ad w ak e-up y es no y es no no y es finish con v ersion go = 0 adif = 1 de vice in no y es finish con v ersion go = 0 adif = 1 w ait 2 t ad sta y in sleep selected channel = rc? sleep no y es instr uction? star t of a/d con v ersion dela y ed 1 instr uction cycle f rom sleep? p o w er - do wn a/d y es no w ait 2 t ad finish con v ersion go = 0 adif = 1 sleep ?
1998 microchip technology inc. preliminary ds40181b -page 45 pic12ce67x 9.0 special features of the cpu what sets a microcontroller apar t f rom other p roces- sors are special circuits to deal with the needs of real - t ime applications . t he pic12ce67x f amily has a host of such f eatures intended to maximiz e system reliabil- ity , minimiz e cost through elimination of e xter nal com- ponents , pro vide po w er sa ving oper ating modes and off er code protection. t hese are: oscillator selection reset - p o w er-on r eset (por) - p o w er-up tim er (pwr t) - oscillator star t-up ti mer (ost) interr upts w atchdog timer (wdt) sleep code protection i d locations in-circuit ser ial prog r amming the pic12ce67x has a w atchdog timer which can be shut off only through con gur ation bits . it r uns off its o wn rc oscillator f or added reliability . there are tw o timers that off er necessar y dela ys on po w er-up . one is the oscillator star t-up timer (ost), intended to k eep the chip in reset until the cr ystal oscillator is stab le . the other is the p o w er-up timer (pwr t), which pro vides a x ed dela y of 72 ms (nominal) on po w er-up only , designed to k eep the par t in reset while the po w er sup- ply stabiliz es . with these tw o timers on-chip , most applications need no e xter nal reset circuitr y . sleep mode is designed to off er a v er y lo w current po w er-do wn mode . t he user can w ak e -u p from sleep through e xter nal reset, w atchdog timer w ak e-up , o r through an interr upt. s e v er al oscillator options are also made a v ailab le to allo w the par t to t the application. t he ext rc oscillator option sa v es system cost while the lp cr ystal option sa v es po w er . a set of con gur a- tion bits are used to select v ar ious options . 9.1 c on guration bits the con gur ation bits can be prog r ammed (read as '0') or left unprog r ammed (read as '1') to select v ar ious de vice con gur ations . these bits are mapped in pro- g r am memor y location 2007h. the user will note that address 2007h is be y ond the user prog r am memor y space . in f act, it belongs to the special test/con gur ation memor y space (2000h - 3fffh), which can be accessed only dur ing prog r amming. figure 9-1: configuration w or d cp1 cp0 cp1 cp0 cp1 cp0 mclre cp1 cp0 pwr te wdte fosc2 fosc1 fosc0 register : config address 2007h bit13 bit0 bit 13-8 , cp1:cp0: code protection bit pairs ( 1) 6-5: 11 = code protection off 10 = locations 400h through 7f eh code protected (do not use f or pic12c e 67 3 ) 01 = locations 200h through 7f eh code protected 00 = all memor y is code protecte d bit 7: mclre : master clear reset enab le bit 1 = master clear enab led 0 = master clear disab led bit 4: pwr te : p o w er-up timer enab le bit 1 = pwr t disab led 0 = pwr t enab led bit 3: wdte : w atchdog timer enab le bit 1 = wdt enab led 0 = wdt disab led bit 2- 0: fosc2:fosc0: oscillator selection bits 111 = extrc , cloc k out on osc2 110 = extrc , osc2 is i/o 101 = intrc , cloc k out on osc2 100 = intrc , osc2 is i/o 011 = in v alid selection 010 = hs oscillator 001 = xt oscillator 000 = lp oscillator note 1: all of the cp1:cp0 pairs ha v e to be giv en the same v alue to enab le the code protection scheme listed.
pic12ce67x ds40181b -page 46 preliminary 1998 microchip technology inc. 9.2 oscillator con gurations 9.2.1 oscillator t ypes the pic12ce67x can be oper ated in se v en diff erent oscillator modes . the user can prog r am t hree c on gur ation bits (fosc 2: fosc0) to select one of these se v en m odes: lp: lo w p o w er cr ystal hs: high speed cr ystal resonator xt : cr ystal/resonator intrc*: i nter nal 4 mhz oscillator extrc*: exter nal resistor/capacitor *can be con gured to suppor t clk out 9.2.2 cr ystal oscillator / cer amic resonators in xt , hs o r lp modes , a cr ystal or cer amic resonator is connected to the gp5/osc1/clkin and gp4/osc2 pins to estab lish oscillation ( figure 9-2 ). the pic12ce67x oscillator design requires the use of a par allel cut cr ystal. use of a ser ies cut cr ystal ma y giv e a frequency out of the cr ystal man uf acturers speci cations . when in xt , hs or lp modes , the de vice can ha v e an e xter nal cloc k source dr iv e the gp5/osc1/clkin pin ( figure 9-3 ). figure 9-2: cr ystal operatio n ( or ceramic resonator) (xt , hs or lp osc configuration) figure 9-3: external cloc k input operation (xt , hs or lp osc configuration) note 1: see capacitor selection tab les f or recommended v alues of c1 and c2. 2: a ser ies resistor (rs) ma y be required f or a t str ip cut cr ystals . 3: rf v ar ies with the cr ystal chosen (appro x. v alue = 10 m w ). c1 (1) c2 (1) xt al osc2 osc1 rf (3) sleep t o inter nal logic rs (2) pic12ce67x cloc k from e xt. system osc1 osc2 pic12ce67x open t ab le 9-1: capacitor selection for ceramic resonator s - pic12ce67x t ab le 9-2: capacitor selection for cr ystal oscillator - pic12ce67x osc t ype resonator freq cap. rang e c1 cap. rang e c2 xt 455 khz 2.0 mhz 4.0 mhz 22-100 pf 15-68 pf 15-68 pf 22-100 pf 15-68 pf 15-68 pf hs 4.0 mhz 8.0 mhz 10.0 mhz 15-68 pf 10-68 pf 10-22 p f 15-68 pf 10-68 pf 10-22 p f these v alues are f or design guidance only . since each resonator has its o wn char acter istics , the user should consult the resonator man uf acturer f or appropr iate v alues of e xter nal components . osc t ype resonator freq cap.rang e c1 cap. rang e c2 lp 32 khz (1) 100 khz 200 khz 15 pf 15-30 pf 15-30 pf 15 pf 30-47 pf 15-82 pf xt 100 khz 200 khz 455 khz 1 mhz 2 mhz 4 mhz 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-47 pf 200-300 pf 100-200 pf 15-100 pf 15-30 pf 15-30 pf 15-47 pf hs 4 mhz 8 mh z 10 mhz 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15-30 pf note 1: f or v dd > 4.5v , c1 = c2 ? 30 pf is recommended. t hese v alues are f or design guidance only . rs ma y be required in hs mode as w ell as xt mode to a v oid o v erdr iving cr ystals with lo w dr iv e le v el speci cation. since each cr ystal has its o wn char acter istics , the user should consult the cr ystal man uf acturer f or appropr iate v alues of e xter nal components .
1998 microchip technology inc. preliminary ds40181b -page 47 pic12ce67x 9.2.3 exter nal cr ystal oscillator circuit either a prepac kaged oscillator or a simple oscillator circuit with ttl gates can be used as an e xter nal cr ystal oscillator circuit. prepac kaged oscillators pro vide a wide oper ating r ange and better stability . a w ell-designed cr ystal oscillator will pro vide good perf or mance with ttl gates . t w o types of cr ystal oscillator circuits can be used: one with par allel resonance , or one with ser ies resonance . figure 9-4 sho ws implementation of a par allel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the cr ystal. the 74as04 in v er ter perf or ms the 180-deg ree phase shift that a par allel oscillator requires . the 4.7 k w resistor pro vides the negativ e f eedbac k f or stability . the 10 k w potentiometers bias the 74as04 in the linear region. this circuit could be used f or e xter nal oscillator designs . figure 9-4: external p arallel resonant cr ystal oscillator cir cuit figure 9-5 sho ws a ser ies resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the cr ystal. the in v er ter perf or ms a 180- deg ree phase shift in a ser ies resonant oscillator circuit. the 330 w resistors pro vide the negativ e f eedbac k to bias the in v er ters in their linear region. figure 9-5: external series resonant cr ystal oscillator cir cuit 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xt al 10k 74as04 pic12ce67x clkin t o other de vices 330 74as04 74as04 pic12ce67x clkin t o other de vices xt al 330 74as04 0.1 m f 9.2.4 external rc oscillator f or timing insensitiv e applications , the rc de vice option off ers additional cost sa vings . the rc oscillator frequency is a function of the supply v oltage , the resistor (re xt) and capacitor (ce xt) v alues , and the oper ating temper ature . in addition to this , the oscillator frequency will v ar y from unit to unit due to nor mal process par ameter v ar iation. fur ther more , the diff erence in lead fr ame capacitance betw een pac kage types will also aff ect the oscillation frequency , especially f or lo w ce xt v alues . the user also needs to tak e into account v ar iation due to toler ance of e xter nal r and c components used. figure 9-6 sho ws ho w the r/c combination is connected to the pic12ce67x . f or re xt v alues belo w 2.2 k w , the oscillator oper ation ma y become unstab le , or stop completely . f or v er y high re xt v alues (e .g., 1 m w ) the oscillator becomes sensitiv e to noise , humidity and leakage . thus , w e recommend k eeping re xt betw een 3 k w and 100 k w . although the oscillator will oper ate with no e xter nal capacitor (ce xt = 0 pf), w e recommend using v alues abo v e 20 pf f or noise and stability reasons . with no or small e xter nal capacitance , the oscillation frequency can v ar y dr amatically due to changes in e xter nal capacitances , such as pcb tr ace capacitance or pac kage lead fr ame capacitance . the electr ical speci cations sections sho w rc frequency v ar iation from par t to par t due to nor mal process v ar iation. the v ar iation is larger f or larger r (since leakage current v ar iation will aff ect rc frequency more f or large r) and f or smaller c (since v ar iation of input capacitance will aff ect rc frequency more). also , see the electr ical speci cations sections f or v ar iation of oscillator frequency due to v dd f or giv en re xt/ce xt v alues as w ell as frequency v ar iation due to oper ating temper ature f or giv en r, c , and v dd v alues . figure 9-6: external rc oscillator mode v dd re xt ce xt v ss osc1 inter nal cloc k pic12ce67x n osc 2/clk out f osc /4
pic12ce67x ds40181b -page 48 preliminary 1998 microchip technology inc. 9.2.5 inter nal 4 mh z rc oscillator the inter nal rc oscillator pro vides a x ed 4 mhz (nom- inal) system cloc k at v dd = 5v and 25 c , see "electr i- cal speci cations" section f or inf or mation on v ar iation o v er v oltage and temper ature . in addition, a calibr ation instr uction is prog r ammed into the last address of the prog r am m emor y which contains the calibr ation v alue f or the inter nal rc oscillator . this v alue is prog r ammed as a retl w xx instr uction where xx is the calibr ation v alue . in order to retr ie v e the cali- br ation v alue , issue a call yy instr uction where yy is the last location in prog r am memor y (03ffh f or the pic12c e 67 3 , 07ffh f or the pic12c e 67 4 ). control will be retur ned to the user s prog r am with the calibr ation v alue loaded into the w register . the prog r am should then perf or m a mo vwf osccal instr uction to load the v alue into the inter nal rc oscillator tr im register . osccal, when wr itten to with the ca libr ation v alue , will ?r im the inter nal oscillator to remo v e process v ar iation from the oscillator frequency . only bits <7:2> of osc- cal are implemented, and bits <1:0> should be wr itten as 0 f or compatibility with future de vices . the oscillator calibr ation location is not code protected. 9.2.6 cl k o ut the pic12c e 67x can be con gured to pro vide a cloc k out signal ( clk out ) on pin 3 when the con gur ation w ord address (2007h) is prog r ammed with fosc2, fosc1, fosc0 equal to 101 f or intrc or 111 f or extrc . the oscillator frequency , divided b y 4 can be used f or test pur poses or to synchroniz e other logic. note: please note that er asing the de vice will also er ase the pre- prog r ammed inter nal calibr ation v alue f or the inter nal oscillator . the calibr ation v alue m ust be sa v ed pr ior to e r asing the par t. 9.3 r eset the pic12ce67x diff erentiates betw een v ar ious kinds of reset: p o w er-on re set (por) mclr reset dur ing nor mal oper ation mclr reset dur ing sleep wdt re set ( n or mal oper ation ) some registers are not aff ected in an y reset condition; their status is unkno wn on por and unchanged in an y other reset. most other registers are reset to a ?eset state on p o w er-on reset (por), m clr reset , w dt reset, and m clr re set dur ing sleep . the y are not aff ected b y a wdt w ak e-up , which is vie w ed as the resumption of nor mal oper ation. the t o and pd bits are set or cleared diff erently in diff erent reset situations as indicated in t ab le 9-4 . these bits are used in softw are to deter mine the nature of the reset. see t ab le 9-5 f or a full descr iption of reset states of all registers . a simpli ed b loc k diag r am of the on-chip reset circuit is sho wn in figure 9-7 . the pic1 2ce67x has a mclr noise lter in the mclr reset path. the lter will detect and ignore small pulses . it should be noted that a wdt reset does not dr iv e mclr pin lo w .
1998 microchip technology inc. preliminary ds40181b -page 49 pic12ce67x figure 9-7: simplified bloc k dia gram of on-c hip reset cir cuit s r q w eak pull-up gp3/ m clr /v pp pin v dd osc1/ wdt module v dd r ise detect ost/pwr t on-chip (1) rc osc wdt time-out p o w er-on reset ost pwr t chip_reset 10 -b it ripple-counter enab le ost enab le pwr t sleep see t ab le 9-3 f or time-out situations . note 1: this is a separ ate oscillator from the rc oscillator of the clkin pin. clkin pin 10-bit ripple -c ounter mclre internal mclr
pic12ce67x ds40181b -page 50 preliminary 1998 microchip technology inc. 9.4 p o wer -on reset (por), p o wer -up timer (pwr t) and oscillator star t-up timer (ost) 9.4.1 p o w er-on reset (por) the on-chip por circuit holds the chip in reset until v dd has reached a high enough le v el f or proper oper a- tion. t o tak e adv antage of the por, just tie the mclr pin t hrough a resistor t o v dd . this will eliminate e xter- nal rc components usually needed to create a p o w er- on re set. a maxim um r ise time f or v dd is speci ed. see electr ical speci cations f or details . when the de vice star ts nor mal oper ation (e xits the reset condition), de vice oper ating par ameters (v oltage , frequency , temper ature , ...) m ust be met to ensure oper ation. if these conditions are not met, the de vice m ust be held in reset until the oper ating conditions are met. f or additional inf or mation, ref er to application note an607, " p o w er-up t roub le shooting . " 9.4.2 p o w er-up tim er (pwr t) the p o w er-up ti mer pro vides a x ed 72 ms nominal time-out on po w er-up only , from the por. the p o w er- up time r oper ates on a n i nter nal rc o scillator . the chip is k ept in reset as long as the pwr t is activ e . the pwr t s time dela y allo ws v dd to r ise to an acceptab le le v el. a con gur ation bit is pro vided to enab le/disab le t he pwr t . the po w er-u p ti me dela y will v ar y from chip to chip due to v dd , temper ature , and process v ar iation. see dc par ameters f or details . 9.4.3 oscillator star t-up timer (ost) the oscillator star t-up tim er (ost) pro vides 1024 oscillator cycle (from osc1 input) dela y after the pwr t dela y is o v er . this ensures t hat the cr ystal oscil- lator or resonator has star ted and stabiliz ed. the ost time-out is in v ok ed only f or xt , lp and hs modes and only on p o w er-on re set or w ak e-up from sleep . 9.4.4 time-out sequence on po w er-up the time-out sequence is as f ollo ws: first pwr t time-out is in v ok ed after the por time dela y has e xpired. then ost is activ ated. the total time-out will v ar y based on oscillator con gur ation and the status of the pwr t . f or e xample , in rc mode with the pwr t disab led, there will be no time-out at all. figure 9-8 , figure 9-9 , and figure 9-10 depict time-out sequences on po w er-up . since the time-outs occur from the por pulse , if mclr is k ept lo w long enough, the time-outs will e xpire . then br inging mclr high will begin e x ecution immediately ( figure 9-9 ). this is useful f or testing pur poses or to synchroniz e more than one pic1 2ce67x de vice oper- ating in par allel. t ab le 9-5 sho ws the reset conditions f or all the regis- ters . 9.4.5 p o w er control (pcon) /status register the po w er control/status register , pcon (address 8eh) has one b it . see figure 4-8 f or register . b it1 is por (p o w er-on reset). it is cleared on a p o w er- on reset and is unaff ected otherwise . the user set this bit f ollo wing a p o w er-on reset. on subsequent resets if por is ?? it will indicate that a p o w er-on reset m ust ha v e occurred . t ab le 9-3: t ime-out in v arious situations t ab le 9-4: status /pcon bits and their significance oscillator con guration p o wer -up w ake -u p fr o m s leep pwr te = 0 pwr te = 1 xt , hs , lp 72 ms + 1 024 t osc 1024 t osc 1024 t osc int rc , extrc 72 ms por t o pd 0 1 1 p o w er-on re set 0 0 x illegal, t o is set on por 0 x 0 illegal, pd is set on por 1 0 u wdt reset 1 0 0 wdt w ak e- up 1 u u mclr reset dur ing nor mal oper ation 1 1 0 mclr reset dur ing sleep or interr upt w ak e-up from sleep
1998 microchip technology inc. preliminary ds40181b -page 51 pic12ce67x t ab le 9-5: reset condition f or s pecial register s t ab le 9-6: initialization conditions f or all register s condition pr ogram counter st a tu s register pcon register p o w er-on reset 000h 0001 1xxx ---- --0 - mclr reset dur ing nor mal oper ation 000h 000 u uu uu ---- --u - mclr reset dur ing sleep 000h 0001 0uuu -- -- -- u- wdt reset dur ing nor mal oper ation 000h 0000 uu uu ---- --u - wdt w ak e-up from sleep pc + 1 uuu0 0uuu ---- --u - interr upt w ak e-up from sleep pc + 1 (1) uuu1 0uuu ---- --u - legend: u = unchanged, x = unkno wn, - = unimplemented bit r ead as '0' . note 1: when the w ak e-up is due to an interr upt and the gie bit is set , t he pc is loaded w ith th e i nterr upt v ector (0004h) . register p o wer -on reset mclr reset s wdt reset w ake-up via wdt or interrupt w xxxx xxxx uuuu uuuu uuuu uuuu indf 0000 0000 0000 0000 0000 0000 tmr0 xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 pc + 1 (2) st a tus 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr xxxx xxxx uuuu uuuu uuuu uuuu gpio 11xx xxxx 11uu uuuu 11uu uuuu pcla th ---0 0000 ---0 0000 ---u uuuu intcon 0000 000x 0000 000u uuuu uqqq ( 1) pir1 -0-- ---- -0-- ---- -q-- - --- ( 4) adcon0 0000 0000 0000 0000 uuuu u qu u (5) option 1111 1111 1111 1111 uuuu uuuu tris --11 1111 --11 1111 --uu uuuu pie1 -0-- ---- -0-- ---- -u-- ---- pcon ---- --0- ---- --u- ---- --u- osccal 1000 00-- uuuu uu-- uuuu uu-- adcon1 ---- -000 ---- -000 ---- -uuu legend: u = unchanged, x = unkno wn, - = unimplemented bit, read as '0', q = v alue depends on condition note 1: one or more bits in intcon and pir1 will be aff ected (to cause w ak e-up). 2: when the w ak e-up is due to an interr upt and the gie bit is set, the pc is loaded with the interr upt v ector (0004h). 3: see t ab le 9-5 f or reset v alue f or speci c condition. 4: if w ak e-up w as due to a/d completing then bit 6 = 1, all other interr upts gener ating a w ak e-up will cause bit 6 = u . 5: if w ak e-up w as due to a/d completing then bit 3 = 0, all other interr upts gener ating a w ak e-up will cause bit 3 = u .
pic12ce67x ds40181b -page 52 preliminary 1998 microchip technology inc. figure 9-8: time-out sequence on p o wer -up ( mclr not tied to v dd ): case 1 figure 9-9: time-out sequence on p o wer -up ( mclr not tied t o v dd ): case 2 figure 9-10: time-out sequence on p o wer -up ( mclr tied to v dd ) t p wrt t o st v dd mclr internal por pwr t time-out ost time-out internal reset v dd mclr internal por pwr t time-out ost time-out internal reset t p wrt t o st t p wrt t o st v dd mclr internal por pwr t time-out ost time-out internal reset
1998 microchip technology inc. preliminary ds40181b -page 53 pic12ce67x figure 9-11: e xternal p o wer -on reset cir cuit ( f or slo w v dd p o wer -up ) note 1: e xter nal p o w er-on re set circuit is required only if v dd po w er-up slope is too slo w . the diode d helps discharge the capacitor quic kly when v dd po w ers do wn. 2: r < 40 k w is recommended to mak e sure that v oltage drop across r does not violate the de vice s electr ical speci cation. 3: r1 = 100 w to 1 k w will limit an y current o wing into mclr from e xter nal capacitor c in the e v ent of mclr / v pp pin break- do wn due to electrostatic discharge ( esd ) or electr ical ov erstress (e os ) . c r1 r d v dd mclr pic12ce67x figure 9-12: external br o wn-out pr otection cir cuit 1 figure 9-13: external br o wn-out pr otection cir cuit 2 note 1: t his circuit will activ ate reset when v dd goes belo w (vz + 0.7v) where vz = zener v oltage . 2: inter nal bro wn-out detection should be disab led when using this circuit. 3: resistors should be adjusted f or the c har- acter istics of the tr ansistor . v dd 33k 10k 4 .3k v dd mclr pic12ce67x note 1: t his bro wn-out circuit is less e xpensiv e , albeit less accur ate . t r ansistor q1 tur ns off when v dd is belo w a cer tain le v el such that: 2: inter nal bro wn-out detection should be disab led , if a v ailab le , when using this circuit. 3: resistors should be adjusted f or the char acter istics of the tr ansistor . v dd r1 r1 + r2 = 0.7v v dd r2 4 .3k pic12ce67x r1 q1 v dd mclr
pic12ce67x ds40181b -page 54 preliminary 1998 microchip technology inc. 9.5 interrupts the re are f our s ources of interr upt: t he interr upt control register (intcon) records individ- ual interr upt requests in ag bits . i t also has individual and global interr upt enab le bits . a global interr upt enab le bit, gie (intcon<7>) enab les (if set) all un-mask ed interr upts or disab les (if cleared) all interr upts . when bit gie is enab led, and an interr upt s ag bit and mask bit are s et, the interr upt will v ector immediately . i ndividual interr upts can be dis- ab led through their corresponding enab le bits in v ar i- ous r egister s . individual interr upt bits are set regardless of the status of the gie bit. the gie bit is cleared on reset. interrupt sour ces tmr0 o v er o w interr upt exter nal interr upt gp2/int pin gpio p or t change interr upts (pins gp0, gp1, gp3 ) a/d int err upt note: individual interr upt ag bits are set regard- less of the status of their corresponding mask bit or the gie bit. the ?etur n from interr upt instr uction, retfie , e xits the interr upt routine as w ell as sets the gie bit, which re-enab le s interr upts . the gp2/int , gpio por t change interr upt and the tmr0 o v er o w interr upt ags are contained in the intco n r egister . the per ipher al interr upt ag adif , is co ntained in the special function register pir1. the corresponding interr upt enab le bit is contained in special function reg- ister pie1, a nd the per ipher al interr upt enab le bit is contained in special function regis ter intcon. when an interr upt is responded to , the gie bit is cleared to disab le an y fur ther interr upt, the retur n address is pushed on to the stac k and the pc is loaded with 0004h. once in the interr upt ser vice routine the source(s) of the interr upt can be deter mined b y polling the interr upt ag bits . the interr upt ag bit(s) m ust be cleared in softw are bef ore re-enab ling interr upts to a v oid recursiv e interr upts . f or e xter nal interr upt e v ents , such as gpio change interr upt, the interr upt latency will be three or f our instr uction cycles . the e xact latency depends when the interr upt e v ent occurs (figure 8-15). the latency is the same f or one or tw o cycle instr uctions . individual inter- r upt ag bits are set regardless of the status of their corresponding mask bit or the gie bit. figure 9-14: i nterrupt logic gp if gp ie t0 if t0 ie gie w ak eup (if in sleep mode) interr upt to cpu peie adif adie intf inte
1998 microchip technology inc. preliminary ds40181b -page 55 pic12ce67x figure 9-15: int pin i nterrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clk out int pin intf ag (intcon<1>) gie bit (intcon<7>) instr uction flo w pc instr uction f etched instr uction e x ecuted interr upt latency pc pc+1 pc+1 0004h 0005h inst (0004h) inst (0005h) dumm y cycle inst (pc) inst (pc+1) inst (pc-1) inst (0004h) dumm y cycle inst (pc) 1 4 5 1 note 1: intf ag is sampled here (e v er y q1). 2: interr upt latency = 3-4 tcy where tcy = instr uction cycle time . latency is the same whether inst (pc) is a single cycle or a 2-cycle instr uction. 3: clk out is a v ailab le only in intrc and extrc oscillator modes . 4: f or minim um width of int pulse , ref er to a c specs . 5: intf is enab led to be set an ytime dur ing the q4-q1 cycles . 2 3
pic12ce67x ds40181b -page 56 preliminary 1998 microchip technology inc. 9.5.1 tmr0 interr upt an o v er o w (ffh ? 00h) in the tmr0 register will set ag bit t 0if (intcon<2>) . the interr upt can be enab led/disab led b y setting/clear ing enab le bit t0ie (intcon<5>) . ( section 7.0 ) 9.5.2 int interr upt exter nal interr upt on gp2/int pin is edge tr iggered: either r ising if bit intedg (option<6>) is set, or f all- ing, if the intedg bit is clear . when a v alid edge appears on the gp2/int pin, ag bit intf (intcon<1>) is set. this interr upt can be disab led b y clear ing enab le bit inte (intcon<4>). flag bit intf m ust be cleared in softw are in the interr upt ser vice rou- tine bef ore re-enab ling this interr upt. the int interr upt can w ak e-up the processor from sleep , if bit inte w as set pr ior to going into sleep . the status of global inter- r upt enab le bit gie decides whether or not the proces- sor br anches to the interr upt v ector f ollo wing w ak e-up . see section 9.8 f or details on sleep mode . 9.5.3 gpio intcon c hange an input change on gp3, gp1 or gp0 s ets ag bit gpi f (intcon<0>) . the interr upt can be enab led/dis- ab led b y setting/clear ing enab le bit gpi e (intcon< 3> ) . ( section 5.1 ) 9.6 conte xt sa ving during interrupts dur ing an interr upt, only the retur n pc v alue is sa v ed on the stac k. t ypically , users ma y wish to sa v e k e y reg- isters dur ing an interr upt i.e ., w register and st a tus register . this will ha v e to be implemented in softw are . the e xample: a) stores the w register . b) stores the st a tus register in bank 0 . c) ex ecutes the isr code . d) restores the st a tus register (and bank select bit) . e) restores the w registe r . example 9-1 store and restore the st a tus and w registers . the register , w_temp , m ust be de ned in both banks and m ust be de ned at the same offset from the bank base address (i.e ., if w_temp is de ned at 0x20 in bank 0, it m ust also be de ned at 0xa0 in bank 1). example 9-1: sa ving st a tus and w register s in ram movwf w_temp ; copy w to temp register, could be bank one or zero swapf status,w ; swap status to be saved into w bcf status,rp0 ; change to bank zero, regardless of current bank movwf status_temp ; save status to bank zero status_temp register : :(isr) : swapf status_temp,w ; swap status_temp register into w ;(sets bank to original state) movwf status ; move w into status register swapf w_temp,f ; swap w_temp swapf w_temp,w ; swap w_temp into w
1998 microchip technology inc. preliminary ds40181b -page 57 pic12ce67x 9.7 w atc hdog timer (wdt) the w atchdog ti mer is a free r unning on-chip rc oscil- lator which does not require an y e xter nal components . this rc oscillator is separ ate from the rc oscillator of the osc1/ clkin pin. that means that the wdt will r un, e v en if the cloc k on the osc1 /clkin and osc2 / clk out pins of the de vice has been stopped, f or e xample , b y e x ecution of a sleep instr uction. dur ing nor mal oper ation, a wdt time-out gener ates a de vice reset (w atchdog timer reset) . if the de vice is in sleep mode , a wdt time - out causes the de vice to w ak e-up and contin ue with nor mal oper ation (w atch- dog timer w ak e-up). the wdt can be per manently disab led b y clear ing c on gur ation bit w dte ( section 9.1 ). 9.7.1 wdt p er iod the wdt has a nominal time-out per iod of 18 ms , (with no prescaler). the time-out per iods v ar y with temper a- ture , v dd and process v ar iations from par t to par t (see dc specs). if longer time-out per iods are desired, a prescaler with a division r atio of up to 1:128 can be assigned to the wdt under softw are control b y wr iting to the option register . thus , time-out per iods up to 2.3 seconds can be realiz ed. the clrwdt and sleep instr uctions clear the wdt and the postscaler , if assigned to the wdt , and pre v ent it from timing out ear ly and gener ating a premature de vice reset condition. the t o bit in the st a tus register will be cleared upon a w atchdog tim er time-out. 9.7.2 wdt prog r amming consider ations it should also be tak en in to account that under w orst case conditions ( v dd = min., t emper ature = max., and max. wdt prescaler) it ma y tak e se v er al seconds bef ore a wdt time-out occurs . note: when the prescaler is assigned to the wdt , alw a ys e x ecute a clrwdt instr uction bef ore changing the prescale v alue , other- wise a wdt reset ma y occur . figure 9-16: w atc hdog timer bloc k dia gram figure 9-17: summar y of w atc hdog timer register s ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h con g. bits (1) mclre cp1 cp 0 pwr te wdt e fos c2 fosc1 fosc0 81h option gppu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used b y the w atchdog timer . note 1: see figure 9-1 f or oper ation of these bits . not all cp0 and cp1 bits are sho wn. f rom tmr0 cloc k source ( figure 7-5 ) t o tmr0 ( figure 7-5 ) p ostscaler wdt timer wdt enab le bit 0 1 m u x psa 8 - to - 1 mux ps2:ps0 0 1 mux psa wdt time-out note: psa and ps2:ps0 are bits in the option register . 8
pic12ce67x ds40181b -page 58 preliminary 1998 microchip technology inc. 9.8 p o wer - do wn mode (sleep) p o w er- do wn mode is entered b y e x ecuting a sleep instr uction. if enab led, the w atchdog timer will be cleared b ut k eeps r unning, the pd bit (s t a tus <3>) i s cleared, the t o (st a tus<4>) bit is set, and the oscillator dr iv er is tur ned off . the i/o por ts maintain the status the y had, bef ore the sleep instr uction w as e x ecuted (dr iving high, lo w , or hi-impedance). f or lo w est current consumption in this mode , place all i /o pins at e ither v dd , or v ss , ensure n o e xter nal cir- cuitr y is dr a wing current from the i/o pin, po w er -d o wn the a/d , disab le e xter nal cloc ks . pull all i/o pins , that are hi-impedance inputs , h igh or lo w e xter nally to a v oid s witching currents caused b y oating inputs . the t 0c ki input if enab led should also be at v dd or v ss f or lo w est current consumption. the contr ib ution from on - c hip pull-ups on gpio should be considered. the mclr pin if enab led m ust be at a logic high le v el ( v ihmc ) . 9.8.1 w ak e-up from sleep the de vice can w ak e up from sleep through one of the f ollo wing e v ents: 1. exter nal reset input on mclr pin . 2. w atchdog timer w ak e-up ( if wdt w as enab led) . 3. gp2/int interr upt, in terr upt gpio por t change , or some p er ipher al interr upts . exter nal mclr reset will cause a de vice reset. all other e v ents are considered a contin uation of prog r am e x ecution and cause a "w ak e-up". the t o and pd bits in the st a tus register can be used to deter mine the cause of de vice reset. the pd bit, which is set on po w er-up , is cleared when sleep is in v ok ed. the t o bit is cleared if a wdt time-out occurred (and caused w ak e-up). t he f ollo wing per ipher al interr upt can w ak e the de vice f rom sleep: 1. a/d con v ersion (when a/d cloc k source is rc). other per ipher als can not gener ate interr upts since dur ing sleep , no on-chip q cloc ks are present. w hen the sleep instr uction is being e x ecuted, the ne xt instr uction (pc + 1) is pre-f etched. f or the de vice to w ak e-up through an interr upt e v ent, the corresponding interr upt enab le bit m ust be set (enab led). w ak e-up is regardless of the state of the gie bit. if the gie bit is clear (disab led), the de vice contin ues e x ecution at the instr uction after the sleep instr uction. if the gie bit is set (enab led), the de vice e x ecutes the instr uction after the sleep instr uction and then br anches to the inter- r upt address (0004h). in cases where the e x ecution of the instr uction f ollo wing sleep is not desir ab le , the user should ha v e a nop after the sleep instr uction. 9.8.2 w ak e-up using interr upts when global interr upts are disab led (gie cleared) and an y interr upt source has both its interr upt enab le bit and interr upt ag bit set, one of the f ollo wing will occur : if the interr upt occurs bef ore the the e x ecution of a sleep instr uction, the sleep instr uction will complete as a nop . theref ore , the wdt and wdt postscaler will not be cleared, the t o bit will not be set and pd bits will not be cleared. if the interr upt occurs during or after the e x ecu- tion of a sleep instr uction, the de vice will imme- diately w ak e up from sleep . the sleep instr uction will be completely e x ecuted bef ore the w ak e-up . theref ore , the wdt and wdt postscaler will be cleared, the t o bit will be set and the pd bit will be cleared. ev en if the ag bits w ere chec k ed bef ore e x ecuting a sleep instr uction, it ma y be possib le f or f lag bits to become set bef ore the sleep instr uction completes . t o deter mine whether a sleep instr uction e x ecuted, test the pd bit. if the pd bit is set, the sleep instr uction w as e x ecuted as a nop . t o ensure that the wdt is cleared, a clrwdt instr uc- tion should be e x ecuted bef ore a sleep instr uction.
1998 microchip technology inc. preliminary ds40181b -page 59 pic12ce67x figure 9-18: w ake-up fr om sleep t hr ough interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clk out(4) gpio pin gpif ag (intcon<0>) gie bit (intcon<7>) instr uction flo w pc instr uction f etched instr uction e x ecuted pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interr upt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dumm y cycle pc + 2 0004h 0005h dumm y cycle t ost (2) pc+2 note 1: xt , hs or lp oscillator mode assumed. 2: t ost = 1024 t osc (dr a wing not to scale) this dela y will not be there f or intrc and extrc osc mode . 3: gie = '1' assumed. in this case after w ak e- up , the processor jumps to the interr upt routine . if gie = '0', e x ecution will contin ue in-line . 4: clk out is not a v ailab le in xt , hs or lp osc modes , b ut sho wn here f or timing ref erence . 9.9 pr ogram v eri cation/code pr otection if the code protection bit(s) ha v e not been pro- g r ammed, the on-chip prog r am memor y can be read out f or v er i cation pur poses . 9.10 id locations f our memor y locations (2000h - 2003h) are designated as id locations where the user can store chec ksum or other code-identi cation n umbers . these locations are not accessib le dur ing nor mal e x ecution b ut are read- ab le and wr itab le dur ing prog r am/v er ify . it is recom- mended that on ly the 4 least signi cant bits of the id location are us ed. 9.11 in-cir cuit serial pr ogramming pic12ce67x microcontrollers can be ser ially pro- g r ammed while in the end application circuit. this is simply done with tw o lines f or cloc k and data, and three other lines f or po w er , g round, and the prog r amming v oltage . this allo ws customers to man uf acture boards with unprog r ammed de vices , and then prog r am the microcontroller just bef ore shipping the product. this also allo ws the most recent r mw are or a custom r m- w are to be prog r ammed. the de vice is placed into a prog r am/v er ify mode b y holding the gp1 and gp0 pins lo w while r aising the mclr ( v pp ) pin from v il to v ihh ( see prog r amming speci cation). gp1 (cloc k) b ecomes the prog r amming cloc k and gp0 (data) b ecomes the prog r amming data. both gp0 a nd gp1 a re schmitt t r igger inputs in this mode . note: microchip does not recommend code pro- tecting windo w ed de vices . after reset, to place the de vice into prog r amming/v er ify mode , the prog r am counter (pc) is at location 00h. a 6- bit command is then supplied to the de vice . depending on the command, 14-bits of prog r am data are then sup- plied to or from the de vice , depending if the command w as a load or a read. f or complete details of ser ial pro- g r amming, please ref er to the pic1 2c e6 7 x prog r am- ming speci cations . figure 9-19: t ypical in- cir cuit s erial pr ogramming connection exter nal connector signals t o nor mal connections t o nor mal connections pic12ce67x v dd v ss mclr / v pp gp1 gp0 +5v 0v v pp clk data i/o v dd
pic12ce67x ds40181b -page 60 preliminary 1998 microchip technology inc. no tes:
1998 microchip technology inc. preliminary ds40181b -page 61 pic12ce67x 10.0 instruction set summar y each pic12c e 67x instr uction is a 14-bit w ord divided into an opcode which speci es the instr uction type and one or more oper ands which fur ther specify the oper ation of the instr uction. the pic12c e 67x instr uc- tion set summar y in t ab le 10-2 lists b yte-oriented , bit- oriented , and literal and contr ol oper ations . t ab le 10- 1 sho ws the opcode eld descr iptions . f or b yte-oriented instr uctions , 'f' represents a le reg- ister designator and 'd' represents a destination desig- nator . the le register designator speci es which le register is to be used b y the instr uction. the destination designator speci es where the result of the oper ation is to be placed. if 'd' i s z ero , the result is placed in the w register . if 'd' i s one , the result is placed in the le register speci ed in the instr uction. f or bit-oriented instr uctions , 'b' represents a bit eld designator which selects the n umber of the bit aff ected b y the oper ation, while 'f' represents the n umber of the le in which the bit is located. f or literal and contr ol oper ations , 'k' represents an eight or ele v en bit constant or liter al v alue . t ab le 10-1: op code field descriptions field description f register le address (0x00 to 0x7f) w w or king register (accum ulator) b bit address within an 8 -b it le register k liter al eld, constant data or label x don't care location (= 0 or 1) t he assemb ler will gener ate code with x = 0 . it is the recommended f or m of use f or c ompatibility with all microchip softw are tools . d destination select; d = 0: store result in w , d = 1: store result in le register f . def ault is d = 1 label label name tos t op of stac k pc prog r am counter pclath prog r am counter high latch gie global interr upt enab le bi t wdt w atchdog timer /c ounter to time-out bi t pd p o w er-do wn bi t dest destination either the w register or the s peci ed register le location [ ] options ( ) contents ? assigned to < > register bit eld ? in the set of i talics user de ned ter m (f ont is cour ier) the instr uction set is highly or thogonal and is g rouped into three basic categor ies: byte -o riented oper ations bit -o riented oper ations literal and contr ol oper ations all instr uctions are e x ecuted within one single instr uc- tion cycle , unless a conditional test is tr ue or the pro- g r am counter is changed as a result of an instr uction. in this case , the e x ecution tak es tw o instr uction cycles with the second cycle e x ecuted as a nop . one instr uc- tion cycle consists of f our oscillator per iods . thus , f or an oscillator frequency of 4 mhz, the nor mal instr uction e x ecution time is 1 m s . if a conditional test is tr ue or the prog r am counter is changed as a result of an instr uc- tion, the instr uction e x ecution time is 2 m s . t ab le 10-2 lists the instr uctions recogniz ed b y the mp asm assemb ler . figure 10-1 sho ws the three gener al f or mats that the instr uctions can ha v e . all e xamples use the f ollo wing f or mat to represent a he xadecimal n umber : 0xhh where h signi es a he xadecimal digit. figure 10-1: general fo rmat f or instructions note: t o maintain upw ard c ompatibility with future pic12c e 67x products , do not use the option and tris instr uctions . byte-oriented le register oper ations 13 8 7 6 0 d = 0 f or destination w opcode d f (file #) d = 1 f or destination f f = 7-bit le register address bit-oriented le register oper ations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit le register address literal and contr ol oper ations 13 8 7 0 opcode k ( liter al) k = 8-bit immediate v alue 13 11 10 0 opcode k ( liter al) k = 11-bit immediate v alue gener al call and goto instr uctions only
pic12ce67x ds40181b -page 62 preliminary 1998 microchip technology inc. 10.1 special functi on register s as sour ce/destination the pic12ce67x s or thogonal instr uction set allo ws read and wr ite of all le registers , including special function registers . there are some special situations the user should be a w are of: 10.1.1 s t a tus as destination if an instr uction wr ites to st a tus , the z, c and dc bits ma y be set or cleared as a result of the instr uction and o v erwr ite the or iginal data bits wr itten. f or e xample , e x ecuting clrf status will clear register st a tus , and then set the z bit lea ving 0000 0100b in the register . 10.1.2 tri s as destination bit 3 o f the tris register alw a ys reads as a '1' since gp3 is an input only pin. this f act c an aff ect some read- modify-wr ite oper a ti ons on the tris register . 10.1.3 pcl as source or destination r ead, wr ite or read-modify-wr ite on pcl ma y ha v e the f ollo wing results: read pc: pcl ? d est wr ite pcl: pcla th ? pch; 8-bit destination v alue ? pcl read-modify-wr ite: pcl ? alu oper and pcla th ? pch; 8-bit result ? pcl where pch = prog r am counter high b yte (not a n addressab le register), pcla th = prog r am counter high holding latch, d est = destination, wreg or f . 10.1.4 bit manipulation all bit manipulation instr uctions are done b y rst read- ing the entire register , oper ating on the selected bit and wr iting the result bac k (read-modify-wr ite). the user should k eep this in mind when oper ating on special function registers , such as por ts .
1998 microchip technology inc. preliminary ds40181b -page 63 pic12ce67x t ab le 10-2: instruction set summar y mnemonic, operands description cyc les 14-bit opcode status aff ected notes ms b ls b byte-oriented file register opera tions add wf and wf clrf clr w comf decf decfsz incf incfsz ior wf mo vf mo vwf nop rlf rrf subwf sw apf xor wf f , d f , d f - f , d f , d f , d f , d f , d f , d f , d f - f , d f , d f , d f , d f , d add w and f and w with f clear f clear w complement f decrement f decrement f , skip if 0 increment f increment f , skip if 0 inclusiv e or w with f mo v e f mo v e w to f no oper ation rotate left f through carr y rotate right f through carr y subtr act w from f sw ap nib b les in f exclusiv e or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0 000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c ,dc ,z z z z z z z z z c c c ,dc ,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit -oriented file register opera tions bcf bsf btfsc btfss f , b f , b f , b f , b bit clear f bit set f bit t est f , skip if clear bit t est f , skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and contr ol opera tions addl w andl w call clr wdt go t o iorl w mo vl w retfie retl w return sleep subl w xorl w k k k - k k k - k - - k k add liter al and w and liter al with w call subroutine clear w atchdog time r go to address inclusiv e or liter al with w mo v e liter al to w retur n from interr upt retur n with liter al in w retur n from subroutine go into standb y mode subtr act w from liter al exc lusiv e o r liter al with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c ,dc ,z z t o , pd z t o , pd c ,dc ,z z note 1: when an i/o register is modi ed as a function of itself ( e .g. , movf portb, 1 ), the v alue used will be that v alue present on the pins themselv es . f or e xample , if the data latch is '1' f or a pin con gured as input and is dr iv en lo w b y an e xter nal de vice , the data will be wr itten bac k with a '0'. 2: if this instr uction is e x ecuted on the tmr0 register (and, where applicab le , d = 1), the prescaler will be cleared if assigned to the timer0 module . 3: if prog r am counter (pc) is modi ed or a conditional test is tr ue , the instr uction requires tw o cycles . t he second cycle is e x ecuted as a nop .
pic12ce67x ds40181b -page 64 preliminary 1998 microchip technology inc. 10.2 instruction descriptions addl w ad d literal and w syntax: [ label ] a ddl w k oper ands: 0 k 255 oper ation: (w) + k ? ( w ) status aff ected: c , dc , z encoding: 11 111x kkkk kkkk descr iption: the contents of the w register are added to the eight bit liter al 'k' a nd the result is placed in the w register . w ords: 1 cycles: 1 example addlw 0x15 bef ore instr uction w = 0x10 after instr uction w = 0x25 add wf ad d w and f syntax: [ label ] add wf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (w) + (f) ? (dest) status aff ected: c , dc , z encoding: 00 0111 dfff ffff descr iption: add the contents of the w register with r egister 'f'. i f 'd' i s 0 the result is stored in the w register . i f 'd' is 1 the result is stored bac k in register 'f' . w ords: 1 cycles: 1 example addwf fsr, 0 bef ore instr uction w = 0x17 fsr = 0xc2 after instr uction w = 0xd9 fsr = 0xc2 andl w and literal with w syntax: [ label ] a ndl w k oper ands: 0 k 255 oper ation: (w) .and . (k) ? ( w ) status aff ected: z encoding: 11 1001 kkkk kkkk descr iption: the contents of w register are and?d with the eight bit liter al 'k'. t he result is placed in the w register . w ords: 1 cycles: 1 example andlw 0x5f bef ore instr uction w = 0xa3 after instr uction w = 0x03 and wf and w with f syntax: [ label ] a nd wf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (w) .and . (f) ? (dest) status aff ected: z encoding: 00 0101 dfff ffff descr iption: and the w register with register 'f'. i f 'd' i s 0 the result is stored in the w register . i f 'd' is 1 the result is stored bac k in register 'f' . w ords: 1 cycles: 1 example andwf fsr, 1 bef ore instr uction w = 0x17 fsr = 0xc2 after instr uction w = 0x17 fsr = 0x02
1998 microchip technology inc. preliminary ds40181b -page 65 pic12ce67x bcf bit clear f syntax: [ label ] b cf f ,b oper ands: 0 f 127 0 b 7 oper ation: 0 ? ( f < b> ) status aff ected: none encoding: 01 00bb bfff ffff descr iption: bit 'b' i n register 'f' i s cleared . w ords: 1 cycles: 1 example bcf flag_reg, 7 bef ore instr uction fla g_reg = 0xc7 after instr uction fla g_reg = 0x47 bsf bit set f syntax: [ label ] b sf f ,b oper ands: 0 f 127 0 b 7 oper ation: 1 ? ( f ) status aff ected: none encoding: 01 01bb bfff ffff descr iption: bit 'b' i n register 'f' i s set. w ords: 1 cycles: 1 example bsf flag_reg, 7 bef ore instr uction fla g_reg = 0x0a after instr uction fla g_reg = 0x8a btfsc b it t est, sk ip if clear syntax: [ label ] b tfsc f ,b oper ands: 0 f 127 0 b 7 oper ation: skip if (f) = 0 status aff ected: none encoding: 0 1 10bb bfff ffff descr iption: if bit ' b' in register ' f' is '0' then the ne xt i nstr uction is skipped. if bit 'b' i s '0' t hen the ne xt instr uction f etched dur ing the current instr uction e x ecution i s discarded , and a nop is e x ecuted instead, making this a 2 cycle instr uction . w ords: 1 cycles: 1(2) example here false true btfsc goto flag,1 process_code bef ore instr uction pc = address here after instr uction if fla g<1> = 0, pc = address true if fla g<1>= 1, pc = address f alse
pic12ce67x ds40181b -page 66 preliminary 1998 microchip technology inc. btfss bit t est f , sk ip if set syntax: [ label ] b tfss f ,b oper ands: 0 f 127 0 b < 7 oper ation: skip if (f) = 1 status aff ected: none encoding: 01 11bb bfff ffff descr iption: if bit 'b' i n register 'f' i s '1' t hen the ne xt instr uction is skipped. if bit 'b' i s '1', then the ne xt instr uction f etched dur ing the current instr uction e x ecution, is discarded and a nop is e x ecuted instead, making this a 2 cycle instr uction. w ords: 1 cycles: 1(2) example here false true btfss goto flag,1 process_code bef ore instr uction pc = address here after instr uction if fla g<1> = 0, pc = address f alse if fla g<1> = 1, pc = address t rue call call subr outine syntax: [ label ] call k oper ands: 0 k 2047 oper ation: (pc)+ 1 ? t os , k ? pc<10:0>, (pcla th<4:3>) ? pc<12:11> status aff ected: none encoding: 10 0kkk kkkk kkkk descr iption: call subroutine . first, retur n address (pc+1) is pushed onto the stac k. the ele v en bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pcla th. call is a tw o cycle instr uction. w ords: 1 cycles: 2 example here call there bef ore instr uction pc = a ddress h ere after instr uction pc = a ddress t here t os = a ddress h ere+1 clrf clear f syntax: [ label ] clrf f oper ands: 0 f 127 oper ation: 00h ? ( f ) 1 ? z status aff ected: z encoding: 00 0001 1fff ffff descr iption: the contents of register 'f' a re cleared and the z bit is set. w ords: 1 cycles: 1 example clrf flag_reg bef ore instr uction fla g_reg = 0x5a after instr uction fla g_reg = 0x00 z = 1 clr w clear w syntax: [ label ] clr w oper ands: none oper ation: 00h ? (w) 1 ? z status aff ected: z encoding: 00 0001 0 000 0011 descr iption: w register i s cleared. zero bit (z) is set. w ords: 1 cycles: 1 example clrw bef ore instr uction w = 0x5a after instr uction w = 0x00 z = 1
1998 microchip technology inc. preliminary ds40181b -page 67 pic12ce67x clr wdt clear w atc hdog timer syntax: [ label ] clr wdt oper ands: none oper ation: 00h ? wdt 0 ? wdt prescaler , 1 ? t o 1 ? pd status aff ected: t o , pd encoding: 00 0000 0110 0100 descr iption: clrwdt instr uction resets the w atch- dog tim er . it also resets the prescaler of the wdt . status bits t o and pd are set. w ords: 1 cycles: 1 example clrwdt bef ore instr uction wdt counter = ? after instr uction wdt counter = 0x00 wdt prescale r = 0 t o = 1 pd = 1 comf complement f syntax: [ label ] comf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: ( f ) ? (dest) status aff ected: z encoding: 00 1001 dfff ffff descr iption: the contents of register 'f' are comple- mented. if 'd' is 0 the result is stored in w . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example comf reg1,0 bef ore instr uction reg1 = 0x13 after instr uction reg1 = 0x13 w = 0xec decf decrement f syntax: [ label ] decf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) - 1 ? (dest) status aff ected: z encoding: 00 0011 dfff ffff descr iption: decrement register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f' . w ords: 1 cycles: 1 example decf cnt, 1 bef ore instr uction cnt = 0x01 z = 0 after instr uction cnt = 0x00 z = 1 decfsz decrement f , sk ip if 0 syntax: [ label ] decfsz f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) - 1 ? ( d est) ; skip if result = 0 status aff ected: none encoding: 00 1011 dfff ffff descr iption: the contents of register 'f' are decre- mented. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. i f the result is 0, the ne xt instr uction, which is already f etched, is discarded. a nop is e x ecuted instead making it a tw o cycle instr uction. w ords: 1 cycles: 1(2) example here decfsz cnt, 1 goto loop continue bef ore instr uction pc = address here after instr uction cnt = cnt - 1 if cnt = 0, pc = address continue if cnt 1 0, pc = address here+1
pic12ce67x ds40181b -page 68 preliminary 1998 microchip technology inc. go t o unconditional branc h syntax: [ label ] go t o k oper ands: 0 k 2047 oper ation: k ? pc<10:0> p cla th<4:3> ? pc<12:11> status aff ected: none encoding: 10 1kkk kkkk kkkk descr iption: goto is an unconditional br anch. the ele v en bit immediate v alue is loaded into pc bits <10:0>. the upper bits of pc are loaded from pcla th<4:3>. goto is a tw o cycle instr uction. w ords: 1 cycles: 2 example goto there after instr uction pc = address there incf increment f syntax: [ label ] incf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) + 1 ? (dest) status aff ected: z encoding: 00 1010 dfff ffff descr iption: the contents of register 'f' a re incre- mented. if 'd' i s 0 the result is placed in the w register . if 'd' i s 1 the result is placed bac k in register 'f'. w ords: 1 cycles: 1 example incf cnt, 1 bef ore instr uction cnt = 0xff z = 0 after instr uction cnt = 0x00 z = 1 incfsz increment f , sk ip if 0 syntax: [ label ] incfsz f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) + 1 ? (dest), skip if result = 0 status aff ected: none encoding: 00 1111 dfff ffff descr iption: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. if the result is 0, the ne xt instr uction, which is already f etched, is discarded. a nop is e x ecuted instead making it a tw o cycle instr uction . w ords: 1 cycles: 1(2) example here incfsz cnt, 1 goto loop continue bef ore instr uction pc = address here after instr uction cnt = cnt + 1 if cnt= 0, pc = address continue if cnt 1 0, pc = address here +1 iorl w inc lusive or literal with w syntax: [ label ] iorl w k oper ands: 0 k 255 oper ation: (w) .or. k ? (w) status aff ected: z encoding: 11 1000 kkkk kkkk descr iption: the contents of the w register is o r?d with the eight bit liter al 'k'. the result is placed in the w register . w ords: 1 cycles: 1 example iorlw 0x35 bef ore instr uction w = 0x9a after instr uction w = 0xbf z = 1
1998 microchip technology inc. preliminary ds40181b -page 69 pic12ce67x ior wf inc lusive or w with f syntax: [ label ] ior wf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (w) .or. (f) ? ( dest) status aff ected: z encoding: 00 0100 dfff ffff descr iption: inclusiv e or the w register with regis- ter 'f'. if 'd' i s 0 the result is placed in the w register . if 'd' i s 1 the result is placed bac k in register 'f'. w ords: 1 cycles: 1 example iorwf result, 0 bef ore instr uction resul t = 0x13 w = 0x91 after instr uction resul t = 0x13 w = 0x93 z = 1 mo vl w mo ve literal to w syntax: [ label ] mo vl w k oper ands: 0 k 255 oper ation: k ? (w) status aff ected: none encoding: 11 00 xx kkkk kkkk descr iption: the eight bit liter al 'k' i s loaded into w register . t he don? cares will assemb le as 0 s . w ords: 1 cycles: 1 example movlw 0x5a after instr uction w = 0x5a mo vf mo ve f syntax: [ label ] mo vf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (f) ? (dest) status aff ected: z encoding: 00 1000 dfff ffff descr iption: the contents of register f is mo v ed to a destination d ependant upon the sta- tus of d. if d = 0, destination is w reg- ister . if d = 1, the destination is le register f itself . d = 1 is useful to test a le register since status ag z is aff ected. w ords: 1 cycles: 1 example movf fsr, 0 after instr uction w = v alue in fsr register z = 1 mo vwf mo ve w to f syntax: [ label ] mo vwf f oper ands: 0 f 127 oper ation: (w) ? (f) status aff ected: none encoding: 00 0000 1fff ffff descr iption: mo v e data from w register to register 'f' . w ords: 1 cycles: 1 example movwf option bef ore instr uction option = 0xff w = 0x4f after instr uction option = 0x4f w = 0x4f
pic12ce67x ds40181b -page 70 preliminary 1998 microchip technology inc. nop no operation syntax: [ label ] nop oper ands: none oper ation: no oper ation status aff ected: none encoding: 00 0000 0xx0 0000 descr iption: no oper ation. w ords: 1 cycles: 1 example nop option load option register syntax: [ label ] option oper ands: none oper ation: ( w ) ? option status aff ected: none encoding: 00 0000 0110 0010 descr iption: the contents of the w register are loaded in the option register . this instr uction is suppor ted f or code com- patibility with pic16c5x products . since option is a readab le/wr itab le register , the user can directly address it. w ords: 1 cycles: 1 example t o maintain upwar d compatibility with future pic12c67x pr oducts, do not use this instruction. retfie return fr om interrupt syntax: [ label ] retfie oper ands: none oper ation: t os ? pc , 1 ? gie status aff ected: none encoding: 00 0000 0000 1001 descr iption: retur n from interr upt. stac k is pop e d and t op of stac k (t os) is loaded in the pc . interr upts are enab led b y set- ting g lobal interr upt enab le bit, g ie ( intcon<7>). this is a tw o cycle instr uction. w ords: 1 cycles: 2 example retfie after interr upt pc = t os gie = 1 retl w return with literal in w syntax: [ label ] retl w k oper ands: 0 k 255 oper ation: k ? ( w ); t os ? pc status aff ected: none encoding: 11 01xx kkkk kkkk descr iption: the w register is loaded with the eight bit liter al 'k'. the prog r am counter is loaded from the top of the stac k (the retur n address). this is a tw o cycle instr uction. w ords: 1 cycles: 2 example table call table ; w contains table ;offset value ? ;w now has table value addwf pc ; w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table bef ore instr uction w = 0x07 after instr uction w = v alue of k 8
1998 microchip technology inc. preliminary ds40181b -page 71 pic12ce67x return return fr om subr outine syntax: [ label ] return oper ands: none oper ation: t os ? pc status aff ected: none encoding: 00 0000 0000 1000 descr iption: retur n from subroutine . the stac k is pop e d and the top of the stac k (t os) is loaded into the prog r am counter . this is a tw o cycle instr uction. w ords: 1 cycles: 2 example return after interr upt pc = t os rlf rotate left f thr ough carr y syntax: [ label ] rlf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: see descr iption b elo w status aff ected: c encoding: 00 1101 dfff ffff descr iption: the contents of register 'f' are rotated one bit to the left through the carr y flag. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is stored bac k in register 'f ' . w ords: 1 cycles: 1 example rlf reg1,0 bef ore instr uction reg1 = 1110 0110 c = 0 after instr uction reg1 = 1110 0110 w = 1100 1100 c = 1 register f c rrf rotate right f thr ough carr y syntax: [ label ] rrf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: see descr iption b elo w status aff ected: c encoding: 00 1100 dfff ffff descr iption: the contents of register 'f' are rotated one bit to the r ight through the carr y flag. if 'd' is 0 the result is placed in the w register . if 'd ' is 1 the result is placed bac k in register 'f' . w ords: 1 cycles: 1 example rrf reg1,0 bef ore instr uction reg1 = 1110 0110 c = 0 after instr uction reg1 = 1110 0110 w = 0111 0011 c = 0 sleep syntax: [ label ] sleep oper ands: none oper ation: 00h ? wdt , 0 ? wdt prescaler , 1 ? t o , 0 ? pd status aff ected: t o , pd encoding: 00 0000 0110 0011 descr iption: the po w er -d o wn status bit , p d i s cleared. time-out status bit , t o i s set. w atchdog timer and its pres- caler are cleared. the processor is put into sleep mode with the oscillator stopped. w ords: 1 cycles: 1 example: sleep register f c
pic12ce67x ds40181b -page 72 preliminary 1998 microchip technology inc. subl w subtract w fr om literal syntax: [ label ] subl w k oper ands: 0 k 255 oper ation: k - (w) ? ( w) status aff ected: c , dc , z encoding: 11 110x kkkk kkkk descr iption: the w register is subtr acted (2 s com- plement method) from the eight bit liter al 'k'. the result is placed in the w register . w ords: 1 cycles: 1 example 1: sublw 0x02 bef ore instr uction w = 1 c = ? after instr uction w = 1 c = 1; result is positiv e example 2: bef ore instr uction w = 2 c = ? after instr uction w = 0 c = 1; result is z ero example 3: bef ore instr uction w = 3 c = ? after instr uction w = 0x ff c = 0; result is nega- tiv e subwf subtract w fr om f syntax: [ label ] subwf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: ( f ) - (w) ? ( dest) status aff ected: c , dc , z encoding: 00 0010 dfff ffff descr iption: subtr act (2 s complement method ) w reg- ister from register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example 1: subwf reg1,1 bef ore instr uction reg1 = 3 w = 2 c = ? after instr uction reg1 = 1 w = 2 c = 1; result is positiv e example 2: bef ore instr uction reg1 = 2 w = 2 c = ? after instr uction reg1 = 0 w = 2 c = 1; result is z ero example 3: bef ore instr uction reg1 = 1 w = 2 c = ? after instr uction reg1 = 0x ff w = 2 c = 0; result is negativ e
1998 microchip technology inc. preliminary ds40181b -page 73 pic12ce67x sw apf swap nibb les in f syntax: [ label ] sw apf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: ( f< 3:0>) ? ( d est < 7:4>) , ( f< 7:4>) ? ( d est < 3:0>) status aff ected: none encoding: 00 1110 dfff ffff descr iption: the upper and lo w er nib b les of regis- ter 'f' are e xchanged. if 'd' is 0 the result is placed in w register . if 'd' is 1 the result is placed in register 'f'. w ords: 1 cycles: 1 example swapf reg, 0 bef ore instr uction reg1 = 0xa5 after instr uction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f oper ands: 5 f 7 oper ation: ( w ) ? tris register f; status aff ected: none encoding: 00 0000 0110 0fff descr iption: the instr uction is suppor ted f or code compatibility with the pic16c5x prod- ucts . since tris registers are read- ab le and wr itab le , the user can directly address them. w ords: 1 cycles: 1 example t o maintain upwar d compatibility with future pic12c67x pr oducts, do not use this instruction. xorl w exc lusive or literal with w syntax: [ label ] xorl w k oper ands: 0 k 255 oper ation: (w) .xor. k ? ( w) status aff ected: z encoding: 11 1010 kkkk kkkk descr iption: the contents of the w register are xor?d with the eight bit liter al 'k'. the result is placed in the w regis- ter . w ords: 1 cycles: 1 example: xorlw 0xaf bef ore instr uction w = 0xb5 after instr uction w = 0x1a xor wf exc lusive or w with f syntax: [ label ] xor wf f ,d oper ands: 0 f 127 d ? [0,1] oper ation: (w) .xor. (f) ? ( dest) status aff ected: z encoding: 00 0110 dfff ffff descr iption: exclusiv e or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example xorwf reg 1 bef ore instr uction reg = 0xaf w = 0xb5 after instr uction reg = 0x1a w = 0xb5
pic12ce67x ds40181b -page 74 preliminary 1998 microchip technology inc. no tes:
1998 microchip technology inc. preliminary ds40181b -page 75 pic12ce67x 11.0 de velopment suppor t 11.1 de velopme nt t ools the picmicr o? microcontrollers are suppor ted with a full r ange of hardw are and softw are de v elopment tools: mplab-ice real-time in-circuit em ulator icepic ? lo w-cost pic16c5x and pic16cxxx in-circuit em ulator pr o ma te a ii univ ersal prog r ammer picst ar t a plus entr y-le v el prototype prog r ammer simice picdem-1 lo w-cost demonstr ation board picdem-2 lo w-cost demonstr ation board picdem-3 lo w-cost demonstr ation board mp asm assemb ler mplab ? sim softw are sim ulator mplab-c17 (c compiler) fuzzy logic de v elopment system ( fuzzy tech a - mp) k ee l oq ? ev aluation kits and prog r ammer 11.2 mplab-ice: high p erf ormance univer sal in-cir cuit em ulator with mplab ide the mplab-ice univ ersal in-circuit em ulator is intended to pro vide the product de v elopment engineer with a complete microcontroller design tool set f or picmicro microcontrollers (mcus). mplab-ice is sup- plied with the mplab integ r ated de v elopment en viron- ment (ide), which allo ws editing, ?ak e and do wnload, and source deb ugging from a single en vi- ronment. interchangeab le processor modules allo w the system to be easily recon gured f or em ulation of diff erent pro- cessors . the univ ersal architecture of the mplab-ice allo ws e xpansion to suppor t all ne w microchip micro- controllers . the mplab-ice em ulator system has been designed as a real-time em ulation system with adv anced f ea- tures that are gener ally f ound on more e xpensiv e de v elopment tools . the pc compatib le 386 (and higher) machine platf or m and microsoft win do ws a 3.x or windo ws 95 en vironment w ere chosen to best mak e these f eatures a v ailab le to y ou, the end user . mplab-ice is a v ailab le in tw o v ersions . mplab- ice 1000 is a basic , lo w-cost em ulator system with simple tr ace capabilities . it shares processor mod- ules with the mplab-ice 2000. this is a full-f eatured em ulator system with enhanced tr ace , tr igger , and data monitor ing f eatures . both systems will oper ate across the entire oper ating speed reange of the picmicro mcu . 11.3 icepic: lo w-cost picmicr o in-cir cuit em ulator icepic is a lo w-cost in-circuit em ulator solution f or the microchip pic12cxxx, pic16c5x and pic16cxxx f amilies of 8-bit o tp microcontrollers . icepic is designed to oper ate on pc-compatib le machines r anging from 386 through p entium ? based machines under windo ws 3.x, windo ws 95, or win- do ws nt en vironment. icepic f eatures real time , non- intr usiv e em ulation. 11.4 pr o ma te ii: univer sal pr ogrammer the pr o ma te ii univ ersal prog r ammer is a full-f ea- tured prog r ammer capab le of oper ating in stand-alone mode as w ell as pc-hosted mode . pr o ma te ii is ce compliant. the pr o ma te ii has prog r ammab le v dd and v pp supplies which allo ws it to v er ify prog r ammed memor y at v dd min and v dd max f or maxim um reliability . it has an lcd displa y f or displa ying error messages , k e ys to enter commands and a modular detachab le soc k et assemb ly to suppor t v ar ious pac kage types . in stand- alone mode the pr o ma te ii can read, v er ify or pro- g r am pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx de vices . it can also set con gur ation and code-protect bits in this mode . 11.5 picst ar t plus entr y le vel de velopment system the picst ar t prog r ammer is an easy-to-use , lo w- cost prototype prog r ammer . it connects to the pc via one of the com (rs-232) por ts . mplab integ r ated de v elopment en vironment softw are mak es using the prog r ammer simple and ef cient. picst ar t plus is not recommended f or production prog r amming. picst ar t plus suppor ts all pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx de vices with up to 40 pins . larger pin count de vices such as the pic16c923, pic16c924 and pic17c756 ma y be sup- por ted with an adapter soc k et. picst ar t plus is ce compliant.
pic12ce67x ds40181b -page 76 preliminary 1998 microchip technology inc. 11.6 simice entr y-le vel har d ware sim ulator simice is an entr y-le v el hardw are de v elopment sys- tem designed to oper ate in a pc-based en vironment with microchip s sim ulator mplab-sim. both sim- ice and mplab-sim r un under microchip t echnol- ogy s mplab integ r ated de v elopment en vironment (ide) softw are . speci cally , simice pro vides hardw are sim ulation f or microchip s pic12c5xx, pic12ce5xx, and pic16c5x f amilies of picmicro 8-bit microcon- trollers . simice w or ks in conjunction with mplab-sim to pro vide non-real-time i/o por t em ulation. simice enab les a de v eloper to r un sim ulator code f or dr iving the target system. in addition, the target system can pro vide input to the sim ulator code . this capability allo ws f or simple and inter activ e deb ugging without ha ving to man ually gener ate mplab-sim stim ulus les . simice is a v aluab le deb ugging tool f or entr y- le v el system de v elopment. 11.7 picdem-1 lo w-cost picmicr o demonstration boar d the picdem-1 is a simple board which demonstr ates the capabilities of se v er al of microchip s microcontrol- lers . the microcontrollers suppor ted are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessar y hardw are and softw are is included to r un basic demo prog r ams . the users can prog r am the sample micro controllers pro vided with the picdem-1 board, on a pr o ma te ii or picst ar t -plus prog r ammer , and easily test r m- w are . the user can also connect the picdem-1 board to the mplab-ice em ulator and do wn load the r mw are to the em ulator f or testing. additional proto- type area is a v ailab le f or the user to b uild some addi- tional hardw are and connect it to the microcontroller soc k et(s). some of the f eatures include an rs-232 interf ace , a potentiometer f or sim ulated analog input, push-b utton s witches and eight leds connected to por tb . 11.8 picdem-2 lo w-cost pic16cxx demonstration boar d the picdem-2 is a simple demonstr ation board that suppor ts the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcon trollers . all the necessar y hardw are and softw are is included to r un the basic demonstr ation prog r ams . the user can prog r am the sample microcontrollers pro vided with the picdem-2 board, on a pr o ma te ii pro- g r ammer or picst ar t -plus , and easily test r mw are . the mplab-ice em ulator ma y also be used with the picdem-2 board to test r mw are . additional prototype area has been pro vided to the user f or adding addi- tional hardw are and connecting it to the microcontroller soc k et(s). some of the f eatures include a rs-232 inter- f ace , push-b utton s witches , a potentiometer f or sim u- lated analog input, a ser ial eepr om to demonstr ate usage of the i 2 c b us and separ ate headers f or connec- tion to an lcd module and a k e ypad. 11.9 picdem-3 lo w-cost pic16cxxx demonstration boar d the picdem-3 is a simple demonstr ation board that suppor ts the pic16c923 and pic16c924 in the plcc pac kage . it will also suppor t future 44-pin plcc microcontrollers with a lcd module . all the neces- sar y hardw are and softw are is included to r un the basic demonstr ation prog r ams . the user can pro- g r am the sample microcontrollers pro vided with the picdem-3 board, on a pr o ma te ii prog r am- mer or picst ar t plus with an adapter soc k et, and easily test r mw are . the mplab-ice em ulator ma y also be used with the picdem-3 board to test r m- w are . additional prototype area has been pro vided to the user f or adding hardw are and connecting it to the microcontroller soc k et(s). some of the f eatures include an rs-232 interf ace , push-b utton s witches , a potenti- ometer f or sim ulated analog input, a ther mistor and separ ate headers f or connection to an e xter nal lcd module and a k e ypad. also pro vided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments , that is capab le of displa ying time , temper ature and da y of the w eek. the picdem-3 pro vides an addi- tional rs-232 interf ace and windo ws 3.1 softw are f or sho wing the dem ultiple x ed lcd signals on a pc . a sim- ple ser ial interf ace allo ws the user to constr uct a hard- w are dem ultiple x er f or the lcd signals .
1998 microchip technology inc. preliminary ds40181b -page 77 pic12ce67x 11.10 mplab integrated de velopment en vir onment software the mplab ide softw are br ings an ease of softw are de v elopment pre viously unseen in the 8-bit microcon- troller mar k et. mplab is a windo ws based application which contains: a full f eatured editor three oper ating modes - editor - em ulator - sim ulator a project manager customizab le tool bar and k e y mapping a status bar with project inf or mation extensiv e on-line help mplab allo ws y ou to: edit y our source les (either assemb ly or ?? one touch assemb le (or compile) and do wnload to picmicro tools (automatically updates all project inf or mation) deb ug using: - source les - absolute listing le the ability to use mplab with microchip s sim ulator allo ws a consistent platf or m and the ability to easily s witch from the lo w cost sim ulator to the full f eatured em ulator with minimal retr aining due to de v elopment tools . 11.11 assemb ler (mp asm) the mp asm univ ersal macro assemb ler is a pc- hosted symbolic assemb ler . it suppor ts all microcon- troller ser ies including the pic12c5xx, pic14000, pic16c5x, pic16cxxx, and pic17cxx f amilies . mp asm off ers full f eatured macro capabilities , condi- tional assemb ly , and se v er al source and listing f or mats . it gener ates v ar ious object code f or mats to suppor t microchip's de v elopment tools as w ell as third par ty prog r ammers . mp asm allo ws full symbolic deb ugging from mplab- ice, microchip s univ ersal em ulator system. mp asm has the f ollo wing f eatures to assist in de v elop- ing softw are f or speci c use applications . pro vides tr anslation of assemb ler source code to object code f or all microchip microcontrollers . macro assemb ly capability . produces all the les (object, listing, symbol, and special) required f or symbolic deb ug with microchip s em ulator systems . suppor ts he x (def ault), decimal and octal source and listing f or mats . mp asm pro vides a r ich directiv e language to suppor t prog r amming of the picmicro . directiv es are helpful in making the de v elopment of y our assemb le source code shor ter and more maintainab le . 11.12 software sim ulator (mplab-sim) the mplab-sim softw are sim ulator allo ws code de v elopment in a pc host en vironment. it allo ws the user to sim ulate the picmicro ser ies microcontrollers on an instr uction le v el. on an y giv en instr uction, the user ma y e xamine or modify an y of the data areas or pro vide e xter nal stim ulus to an y of the pins . the input/ output r adix can be set b y the user and the e x ecution can be perf or med in; single step , e x ecute until break, or in a tr ace mode . mplab-sim fully suppor ts symbolic deb ugging using mplab-c17 and mp asm. the softw are sim ulator off ers the lo w cost e xibility to de v elop and deb ug code outside of the labor ator y en vironment making it an e xcellent m ulti-project softw are de v elopment tool. 11.13 mplab-c17 compiler the mplab-c17 code de v elopment system is a complete ansi ? compiler and integ r ated de v elop- ment en vironment f or microchip s pic17cxxx f amily of microcontrollers . the compiler pro vides po w erful inte- g r ation capabilities and ease of use not f ound with other compilers . f or easier source le v el deb ugging, the compiler pro- vides symbol inf or mation that is compatib le with the mplab ide memor y displa y . 11.14 fuzzy logic de velopment system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic de v elopment tool is a v ail- ab le in tw o v ersions - a lo w cost introductor y v ersion, mp explorer , f or designers to gain a comprehensiv e w or king kno wledge of fuzzy logic system design; and a full-f eatured v ersion, fuzzy tech-mp , edition f or imple- menting more comple x systems . both v ersions include microchip s fuzzy lab ? demon- str ation board f or hands-on e xper ience with fuzzy logic systems implementation. 11.15 seev al a ev aluation and pr ogramming system the seev al seepr om designer s kit suppor ts all microchip 2-wire and 3-wire ser ial eepr oms . the kit includes e v er ything necessar y to read, wr ite , er ase or prog r am special f eatures of an y microchip seepr om product including smar t ser ials ? and secure ser ials . the t otal endur ance ? disk is included to aid in tr ade- off analysis and reliability calculations . the total kit can signi cantly reduce time-to-mar k et and result in an optimiz ed system.
pic12ce67x ds40181b -page 78 preliminary 1998 microchip technology inc. 11.16 k ee l oq a ev aluation and pr ogramming t ools k ee l oq e v aluation and prog r amming tools suppor t microchips hcs secure data products . the hcs e v al- uation kit includes an lcd displa y to sho w changing codes , a decoder to decode tr ansmissions , and a pro- g r amming interf ace to prog r am test tr ansmitters .
1998 microchip technology inc. preliminary ds40181b -page 79 pic12ce67x t ab le 11-1: de velopment t ools fr om micr oc hip pic12c5xx pic14000 pic16c5x pic16cxxx pic16c6x pic16c7xx pic16c8x pic16c9xx pic17c4x pic17c7xx 24cxx 25cxx 93cxx hcs200 hcs300 hcs301 emulator products mplab-ice icepic ? low-cost in-circuit emulator software tools mplab ? integrated development environment mplab ? c17* compiler fuzzy tech a -mp explorer/edition fuzzy logic dev. tool total endurance ? software model pr ogrammer s picstart a plus low-cost universal dev. kit pro mate a ii universal programmer keeloq a programmer demo boards seeval a designers kit simice picdem-14a picdem-1 picdem-2 picdem-3 k ee l oq evaluation kit k ee l oq transponder kit
pic12ce67x ds40181b -page 80 preliminary 1998 microchip technology inc. notes:
1998 microchip technology inc. preliminary ds40181b -page 81 pic12ce67x 12.0 e lectrical characteristics f or pic1 2ce67x absolute maxim um ratings ? ambie nt temper ature under bias ............................................................................................................. . ?0 to +125 c stor age temper ature ............................................................................................................................. ?5 c to +150 c v oltage on an y pin with respect to v ss (e xcept v dd and mclr ) ................................................... ?.3v to ( v dd + 0.3v) v o lt age on v dd with respect to v ss ................................................................................................................ 0 to +7.0v v olt a ge on mclr w ith respect to v ss (note 2) .................................................................................................. 0 to +14v t ot a l po w er dissipation (note 1) ........................................................................................................................... 7 00 mw ma x im um current out of v ss pin ........................................................................................................................... 150 m a m a xim um current into v dd pin .............................................................................................................................. 1 25 m a input clamp current, i ik ( v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma ma x im um output current sunk b y an y i/o pin .......................................................................................................... 25 ma ma x im um output current sourced b y an y i/o pin .................................................................................................... 2 5 m a m a xim um current sunk b y gpio pi ns combined ................................................................................................... 1 00 m a maxi m um current sourced b y gpio pi ns combined .............................................................................................. 10 0 m a note 1: p o w er dissipation is calculated as f ollo ws: pdis = v dd x { i dd - ? i oh } + ? {( v dd - v oh ) x i oh } + ? ( v o l x i ol ) . ? no tice: s tresses abo v e those listed under ?bsolute maxim um ratings ma y cause per manent damage to the de vice . t his is a stress r ating only and functional oper ation of the de vice at those or an y other conditions abo v e those indicated in the oper ation listings of this speci cation is not implied. e xposure to maxim um r ating conditions f or e xtended per iods ma y aff ect de vice reliability .
pic12ce67x ds40181b -page 82 preliminary 1998 microchip technology inc. t ab le 12-1: cr oss ref erence of de vice specs f or oscillator configurations and frequencies of operation (commer cial de vices) osc pic12ce673-04 pic12ce674-04 pic12ce673-10 pic12ce674-10 pic12lce673-04 pic12lce674-04 pic12ce673/jw pic12ce674/jw intrc v dd : 3.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v f req: 4 mhz max. v dd : 3.0v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 2.5v to 5.5v i dd : 2.0 ma typ . at 2.5v i pd : 0.9 m a typ . at 2.5v f req: 4 mhz max. v dd : 3.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v f req: 4 mhz max. extrc v dd : 3.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v f req: 4 mhz max. v dd : 3.0v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 2.5v to 5.5v i dd : 2.0 ma typ . at 2.5v i pd : 0.9 m a typ . at 2.5v f req: 4 mhz max. v dd : 3.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v f req: 4 mhz max. xt v dd : 3.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v f req: 4 mhz max. v dd : 3.0v to 5.5v i dd : 2.7 ma typ . at 5.5v i pd : 1.5 m a typ . at 4v f req: 4 mhz max. v dd : 2.5v to 5.5v i dd : 2.0 ma typ . at 2.5v i pd : 0.9 m a typ . at 2.5v f req: 4 mhz max. v dd : 3.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 21 m a max. at 4v f req: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v n/a v dd : 3.0v to 5.5v i dd : 13.5 ma typ . at 5.5v i dd : 30 ma max. at 5.5v i dd : 30 ma max. at 5.5v i pd : 1.5 m a typ . at 4.5v i pd : 1.5 m a typ . at 4.5v i pd : 1.5 m a typ . at 4.5v f req: 4 mhz max. f req: 10 mhz max. f req: 10 mhz max. lp v dd : 3.0v to 5.5v i dd : 52.5 m a typ . at 32 khz, 4.0v i pd : 0.9 m a typ . at 4.0v f req: 200 khz max. n/a v dd : 2.5v to 5.5v i dd : 48 m a max. at 32 khz, 2.5v i pd : 5.0 m a max. at 2.5v f req: 200 khz max. v dd : 3.0v to 5.5v i dd : 48 m a max. at 32 khz, 2.5v i pd : 5.0 m a max. at 2.5v f req: 200 khz max. the shaded sections indicate oscillator selections which are tested f or functionality , b ut not f or min/max speci cations . it is recommended that the user select the de vice type that ensures the speci cations required.
1998 microchip technology inc. preliminary ds40181b -page 83 pic12ce67x 12.1 dc characteristics: pic12ce673-04 (commer cial, industrial, extended (5) ) pic12ce673-10 (commer cial, industrial, extended (5) ) pic12ce674-04 (commer cial, industrial, extended (5) ) pic12ce674-10 (commer cial, industrial, extended (5) ) * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. note 1: this is the limit to which v dd can be lo w ered in sleep mode without losing ram data. 2: the supply current is mainly a function of the oper ating v oltage and frequency . o ther f actors such as i/o pin loading and s witching r ate , oscillator type , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current c onsumption. the test conditions f or all i dd measurements in activ e oper ation mode are: osc1 = e xter nal square w a v e , from r ail to r ail; all i/o pins t r istated, pulled to v dd mclr = v dd ; wdt enab led/disab led as speci ed. 3: the po w er -d o wn current in sleep mode does not depend on the oscillator type . p o w er -d o wn current is measured with the par t in sleep mode , with all i/o pins in hi-imped an ce state and tied to v dd and v ss . 4: f or extrc osc con gur ation, current through re xt is not included. the current through the resistor can be estimated b y the f or m ula ir = v dd /2re xt (ma) with re xt in kohm. 5: extended oper ating r ange is adv ance inf or mation f or this de vice . 6: intrc calibr ation v alue is f or 4 mhz nominal at 5v , 35 c . dc chara cteristics standar d operating conditions (unless otherwise speci ed) oper ating temper ature 0?c t a +70?c (commercial) ?0?c t a +85?c (industr ial) ? 0 c t a +125 ?c (e xtended) p arm no. characteristic sym min t yp? max units conditions d001 d001a supply v oltage v dd 3.0 4.5 - - 5.5 5.5 v v xt , intrc , extrc and lp osc con gur a- tio n hs osc con gur ation d002 ram data retention v oltage (note 1) v dr - 1.5 - v de vice in sleep mode d003 v dd star t v oltage to ensure inter nal p o w er-on reset signal v po r v ss - v ss v see section on p o w er-on reset f or details d004 v dd r ise r ate to ensure inter- nal p o w er-on reset signal s vd d 0.05 - - v/ms see section on p o w er-on reset f or details d010 d010a d013 supply current (note 2) no read/wr ite to eepr om per ipher al i dd - - 2.7 2 .7 tbd 3. 3 3. 3 15 ma ma ma xt, extrc osc con gur ation (pic12ce67x-04) f osc = 4 mhz, v dd = 5.5v (note 4) intrc osc con gur ation f osc = 4 mhz, v dd = 5.5v (note 6) hs osc con gur ation (pic12ce67x-10) f osc = 10 mhz, v dd = 5.5v d028 d i ee 0 .1 0 .2 v dd = 5.5v scl = 400 khz d020 d021 d021a d021b p o w er-do wn current (note 3) i pd - - - - 5.5 1.5 1.5 1.5 32 16 14 tbd m a m a m a m a v dd = 4.0v , wdt enab led, ?0 c to +85 c v dd = 4.0v , wdt disab led, 0 c to +70 c v dd = 4.0v , wdt disab led, ?0 c to +85 c v dd = 4.0v , wdt disab led, ?0 c to +125 c
pic12ce67x ds40181b -page 84 preliminary 1998 microchip technology inc. 12.2 dc characteristics: pic12lce673-04 (commer cial, industrial) pic12lce674-04 (commer cial, industrial) d c chara cteristics standar d operating conditions (unless otherwise speci ed) oper ating temper ature 0?c t a +70?c (commercial) ?0?c t a +85?c (industr ial) p aram no. characteristic sym min t yp? max units conditions d001 supply v oltage v dd 2.5 - 5.5 v xt , intrc , extrc and lp osc con gur ation (dc - 4 mhz) d002 * ram data retention v oltage (note 1) v dr - tbd - v de vice in sleep mode d003 v dd star t v oltage to ensure inter nal p o w er-on res et signal v por - v ss - v see section on p o w er-on res et f or details d004 * v dd r ise r ate to ensure inter nal p o w er- on res et signal s vdd tbd - - v/ms see section on p o w er-on res et f or details d010 d010b d010a supply current ( note 2) i dd - - tbd tbd tbd tbd tbd tbd ma ma m a xt, extrc osc con gur ation f osc = 4 mhz, v dd = 3.0v (note 4 ) intrc osc con gur ation f osc = 4 mhz, v dd = 3.0v (note 5) lp osc con gur ation f osc = 32 kh z, v dd = 3.0v , wdt disab led d020 d021 d021a p o w er -do wn current (note 3) i pd - - - tbd tbd tbd m a m a m a v dd = 3.0v , wdt enab led, ? 0 c to +85 c v dd = 3.0v , wdt disab led, 0 c to +70 c v dd = 3.0v , wdt disab led, ? 0 c to +85 c * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25?c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. note 1: this is the limit to which v dd can be lo w ered in sleep mode without losing ram data. 2: the supply current is mainly a function of the oper ating v oltage and frequency . o ther f actors such as i/o pin loading and s witching r ate , oscillator type , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current c onsumption. the test conditions f or all i dd measurements in activ e oper ation mode are: osc1 = e xter nal square w a v e , from r ail to r ail; all i/o pins t r istated, pulled to v dd mclr = v dd ; wdt enab led/disab led as speci ed. 3: the po w er -d o wn current in sleep mode does not depend on the oscillator type . p o w er -d o wn current is measured with the par t in sleep mode , with all i/o pins in hi-imped an ce state and tied to v dd and v ss . 4: f or extrc osc con gur ation, current through re xt is not included. the current through the resistor can be estimated b y the f or m ula ir = v dd /2re xt (ma) with re xt in kohm. 5: intrc calibr ation v alue is f or 4 mhz nominal at 5v , 25 c .
1998 microchip technology inc. preliminary ds40181b -page 85 pic12ce67x 12.3 dc characteristics: pic12ce67 3 -04 (commer cial, industrial, extended (4) ) pic12ce67 3 -10 (commer cial, industrial, extended (4) ) pic12ce67 4 -04 (commer cial, industrial, extended (4) ) pic12ce67 4 -10 (commer cial, industrial, extended (4) ) dc chara cteristics standar d operating conditions (unless otherwise speci ed) oper ating temper ature 0?c t a +70?c (commercial) ?0?c t a +85?c (industr ial) ? 0 c t a +125 ?c (e xtended) oper ating v oltage v dd r ange as descr ibed in dc spec section 12.1 and section 12.2 . p aram no. characteristic sym min t yp ? max units conditions input lo w v olta g e i/o por ts v il d030 with ttl b uff er v ss - 0.5v v d031 with schmitt t r igger b uff er v ss - 0.2v dd v d032 mclr , gp2/t0cki/an2/int (in ext rc mode) v ss - 0.2v dd v d033 osc1 (in xt , hs and lp) v ss - 0.3v dd v note1 input high v olta g e i/o por ts v ih - d040 with ttl b uff er 2.0 - v dd v 4.5 v dd 5.5v d040a 0.8v dd - v dd v f or v dd > 5.5v or v dd < 4.5v d041 with schmitt t r igger b uff er 0.8v dd - v dd v f or entire v dd r ange d042 mclr , gp2/t0cki/an2/int 0.8v dd - v dd v d042a osc1 (xt , hs and lp) 0.7v dd - v dd v note1 d043 osc1 (in extrc mode) 0.9v dd - v dd v d070 gpio w eak pull-up current i pur 50 250 400 m a v dd = 5v , v pin = v ss input leaka g e current (notes 2, 3) d060 i/o por ts i il - - + 1 m a vss v pin v dd , pin at hi- impedance d061 mclr , gp2/ t0cki - - + 5 (5) m a vss v pin v dd d063 osc1 - - + 5 m a vss v pin v dd , xt , hs and lp osc con gur ation output lo w v olta g e d080 i/o por ts /clk out v ol - - 0.6 v i ol = 8.5 ma, v dd = 4.5v , ?0 c to +85 c d080a - - 0.6 v i ol = 7.0 ma, v dd = 4 .5v , ?0 c to +125 c d083 osc2 - - 0.6 v i ol = 1.6 ma, v dd = 4 .5v , ?0 c to +85 c d083a - - 0.6 v i ol = 1.2 ma, v dd = 4 .5v , ?0 c to +125 c ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: in extrc os cillator con gur ation, the osc1/clkin pin is a schmitt t r igger input. it is not recommended that the pic12c67x be dr iv en with e xter nal cloc k in rc mode . 2: the leakage current on the mclr pin is strongly dependent on the applied v oltage le v el. the speci ed le v els represent nor mal oper ating conditions . higher leakage current ma y be measured at diff erent input v oltages . 3: negativ e current is de ned as coming out of the pin. 4: extended operating rang e is ad v ance inf ormation f or this de vice . 5: when con gured as e xter nal reset, the input leakage current is the w eak pulll-up current of -10ma minim um. this pull-up is w eak er than the standard i/o pull-up .
pic12ce67x ds40181b -page 86 preliminary 1998 microchip technology inc. output high v olta g e d090 i/o por ts /clk out (note 3) v oh v dd - 0.7 - - v i oh = -3.0 ma, v dd = 4.5v , ?0 c to +85 c d090a v dd - 0.7 - - v i oh = -2.5 ma, v dd = 4.5v , ?0 c to +125 c d092 osc2 v dd - 0.7 - - v i oh = -1.3 ma, v dd = 4.5v , ?0 c to +85 c d092a v dd - 0.7 - - v i oh = -1.0 ma, v dd = 4.5v , ?0 c to +125 c capacitive loading specs on output pins d100 osc2 pin c osc2 - - 15 pf in xt , hs and lp modes when e xter nal cloc k is used to dr iv e osc1. d101 all i/o pins and osc2 c i o - - 5 0 p f dc chara cteristics standar d operating conditions (unless otherwise speci ed) oper ating temper ature 0?c t a +70?c (commercial) ?0?c t a +85?c (industr ial) ? 0 c t a +125 ?c (e xtended) oper ating v oltage v dd r ange as descr ibed in dc spec section 12.1 and section 12.2 . p aram no. characteristic sym min t yp ? max units conditions ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: in extrc os cillator con gur ation, the osc1/clkin pin is a schmitt t r igger input. it is not recommended that the pic12c67x be dr iv en with e xter nal cloc k in rc mode . 2: the leakage current on the mclr pin is strongly dependent on the applied v oltage le v el. the speci ed le v els represent nor mal oper ating conditions . higher leakage current ma y be measured at diff erent input v oltages . 3: negativ e current is de ned as coming out of the pin. 4: extended operating rang e is ad v ance inf ormation f or this de vice . 5: when con gured as e xter nal reset, the input leakage current is the w eak pulll-up current of -10ma minim um. this pull-up is w eak er than the standard i/o pull-up .
1998 microchip technology inc. preliminary ds40181b -page 87 pic12ce67x 12.4 dc characteristics: pic12lce671-04 (commer cial, industrial) pic12lce672-04 (commer cial, industrial) dc chara cteristics standar d operating conditions (unless otherwise speci ed) oper ating temper ature 0?c t a +70?c (commercial) ?0?c t a +85?c (industr ial) oper ating v oltage v dd r ange as descr ibed in dc spec section 12.1 and section 12.2 . p aram no. characteristic sym min t yp ? max units conditions input lo w v olta g e i/o por ts v il d030 with ttl b uff er v ss - tbd v d031 with schmitt t r igger b uff er v ss - tbd v d032 mclr , gp2/t0cki/an2/int (in ext rc mode) v ss - tbd v d033 osc1 (in xt , hs and lp) v ss - tbd v note1 input high v olta g e i/o por ts v ih - d040 with ttl b uff er tbd - v dd v 4.5 v dd 5.5v d040a tbd - v dd v f or v dd > 5.5v or v dd < 4.5v d041 with schmitt t r igger b uff er tbd - v dd v f or entire v dd r ange d042 mclr , gp2/t0cki/an2/int tbd - v dd v d042a osc1 (xt , hs and lp) tbd - v dd v note1 d043 osc1 (in extrc mode) tbd - v dd v d070 gpio w eak pull-up current i pur tbd tbd tbd m a v dd = 5v , v pin = v ss input leaka g e current (notes 2, 3) d060 i/o por ts i il - tbd tbd m a vss v pin v dd , pin at hi- impedance d061 mclr , gp3 - tbd tbd m a vss v pin v dd d063 osc1 - tbd tbd m a vss v pin v dd , xt , hs and lp osc con gur ation output lo w v olta g e d080 i/o por ts /clk out v ol - tbd 0.6 v i ol = tbd , v dd = 4.5v , ?0 c to +85 c d080a - tbd 0.6 v i ol = tbd , v dd = 4.5v , ?0 c to +125 c d083 osc2 - tbd 0.6 v i ol = tbd , v dd = 4.5v , ?0 c to +85 c d083a - tbd 0.6 v i ol = tbd , v dd = 4.5v , ?0 c to +125 c output high v olta g e d090 i/o por ts /clk out (note 3) v oh v dd - 0.7 - - v i oh = tbd , v dd = 4.5v , ?0 c to +85 c d090a v dd - 0.7 - - v i oh = tbd , v dd = 4.5v , ?0 c to +125 c d092 osc2 v dd - 0.7 - - v i oh = tbd , v dd = 4.5v , ?0 c to +85 c d092a v dd - 0.7 - - v i oh = tbd , v dd = 4.5v , ?0 c to +125 c ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: in extrc os cillator con gur ation, the osc1/clkin pin is a schmitt t r igger input. it is not recommended that the pic12c67x be dr iv en with e xter nal cloc k in rc mode . 2: the leakage current on the mclr pin is strongly dependent on the applied v oltage le v el. the speci ed le v els represent nor mal oper ating conditions . higher leakage current ma y be measured at diff erent input v oltages . 3: negativ e current is de ned as coming out of the pin. 4: extended operating rang e is ad v ance inf ormation f or this de vice .
pic12ce67x ds40181b -page 88 preliminary 1998 microchip technology inc. capacitive loading specs on output pins d100 osc2 pin c osc2 - - 15 pf in xt , hs and lp modes when e xter nal cloc k is used to dr iv e osc1. d101 all i/o pins and osc2 c i o - - 5 0 p f dc chara cteristics standar d operating conditions (unless otherwise speci ed) oper ating temper ature 0?c t a +70?c (commercial) ?0?c t a +85?c (industr ial) oper ating v oltage v dd r ange as descr ibed in dc spec section 12.1 and section 12.2 . p aram no. characteristic sym min t yp ? max units conditions ? data in ? yp column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. note 1: in extrc os cillator con gur ation, the osc1/clkin pin is a schmitt t r igger input. it is not recommended that the pic12c67x be dr iv en with e xter nal cloc k in rc mode . 2: the leakage current on the mclr pin is strongly dependent on the applied v oltage le v el. the speci ed le v els represent nor mal oper ating conditions . higher leakage current ma y be measured at diff erent input v oltages . 3: negativ e current is de ned as coming out of the pin. 4: extended operating rang e is ad v ance inf ormation f or this de vice .
1998 microchip technology inc. preliminary ds40181b -page 89 pic12ce67x 12.5 t iming p arameter symbology the timing par ameter symbols ha v e been created f ollo wing one of the f ollo wing f or mats: figure 12-1: load conditions 1. tpps2pps 3. t cc : st (i 2 c speci cations only) 2. tpps 4. ts (i 2 c speci cations only) t f f requency t time lo w ercase letters ( pp) and their meanings: pp cc ccp1 os c osc1 c k clk out rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o por t t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f f all p p er iod h high r rise i in v alid (hi-imped a nce) v v alid l l o w z hi -i mped a nce i 2 c onl y aa output access high high b uf bus free lo w lo w t cc : st (i 2 c speci cations only) cc hd hold su setup st d a t d a t a input hold st o st op condition st a st ar t condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 p f f or all pins e xcept osc 2 15 pf f or osc2 output load condition 1 load condition 2
pic12ce67x ds40181b -page 90 preliminary 1998 microchip technology inc. 12.6 t iming dia grams and speci cations figure 12-2: external cloc k timing t ab le 12-2: cloc k timing requirements p arameter no. sym characteristic min t yp? max units conditions f osc external clkin frequenc y (note 1) dc 4 mhz xt and extrc osc mode dc 4 mhz hs osc mode ( pic 12ce67x -04) dc 10 mhz hs osc mode ( pic 12ce67x -10) dc 200 khz lp osc mode oscillator frequenc y (note 1) dc 4 mhz extrc osc mode .455 4 mhz xt osc mode 4 4 mhz hs osc mode ( pic 12ce67x -04) 4 10 mhz hs osc mode ( pic 12ce67x -10) 5 200 khz lp osc mode 1 t osc external clkin p eriod (note 1) 250 ns xt and extrc osc mode 250 ns hs osc mode ( pic 12ce67x -04) 100 n s hs osc mode ( pic 12ce67x -10) 5 m s lp osc mode oscillator p eriod (note 1) 250 ns extrc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode ( pic 12ce67x -04) 100 250 ns hs osc mode ( pic 12ce67x -10) 5 m s lp osc mode 2 t cy instruction cyc le time (note 1) 400 dc ns t cy = 4/ f osc 3 t osl, t osh external c loc k in (osc1) high or lo w time 50 ns xt oscillator 2.5 m s lp oscillator 10 ns hs oscillator 4 t osr, t osf external cloc k in (osc1) rise or f all time ? 25 ns xt oscillator ? 50 ns lp oscillator 15 ns hs oscillator ? data in "t yp" column is at 5v , 25 c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. note 1: instr uction cycle per iod ( t cy ) equals f our times the input oscillator time -b ase per iod. a ll speci ed v alues are based on char acter ization data f or that par ticular oscillator type under standard oper ating conditions with the de vice e x ecuting code . e xceeding these speci ed limits ma y result in an unstab le oscillator oper ation and/or higher than e xpected current con- sumption. a ll de vices are tested to oper ate at "min." v alues with an e xter nal cloc k applied to the osc1 /clkin pin. when an e xter nal cloc k input is used, the "max." cycle time limit is "dc" (no cloc k) f or all de vices . osc2 is disconnected (has no loading) f or the pic 12ce67x . osc1 clk out q4 q1 q2 q3 q4 q1 1 2 3 3 4 4
1998 microchip technology inc. preliminary ds40181b -page 91 pic12ce67x t ab le 12-3: calibrated internal rc frequencies - pic12c508/c509 a c characteristics standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial), ?0 c t a +85 c (industr ial), ?0 c t a +125 c (e xtended) oper ating v oltage v dd r ange is descr ibed in section 10.1 p arameter no. sym characteristic min* t yp (1) max* units conditions inter nal calibr ated rc f requency tbd 4.00 tbd mhz v dd = 5.0v inter nal calibr ated rc f requency tbd 4.00 tbd mhz v dd = 2.5v * these par ameters are char acter iz ed b ut not tested. note 1: data in the t ypical (? yp? column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested.
pic12ce67x ds40181b -page 92 preliminary 1998 microchip technology inc. figure 12-3: c lk o ut and i/o timing t ab le 12-4: clk out and i/o timing requirements p arameter no. sym characteristic min t yp? max units conditions 10 * t osh2c kl osc1 - to clk out 15 30 ns note 1 11 * t osh2c kh osc1 - to clk out - 15 30 ns note 1 12 * tc kr clk out r ise time 5 15 ns note 1 13 * tc kf clk out f all time 5 15 ns note 1 14 * tc kl2iov clk out to p or t out v alid 0.5 t cy + 20 ns note 1 15 * tiov2c kh p or t in v alid bef ore clk out - 0.25 t cy + 25 ns note 1 16 * tc kh2ioi p or t in hold after clk out - 0 ns note 1 17 * t osh2iov osc1 - (q1 cycle) to p or t out v alid 80 - 100 ns 18 * t osh2ioi osc1 - (q2 cycle) to p or t input i n v ali d ( i/o in hold time) tbd ns 19 * tiov2osh p or t input v alid to osc1 - (i/o in setup time) tbd ns 20 * tior p or t output r ise time pic 12ce67 x 10 25 ns 21 * tiof p or t output f all time pic 12ce67 x 10 25 ns 22?? * tinp int pin high or lo w time 20 ns 23?? * t rbp gpio change int high or lo w time 20 ns * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. ?? these par ameters are asynchronous e v ents not related to an y inter nal cloc k edges . note 1: measurements are tak en in extrc and intrc mo de s where clk out output is 4 x t osc . note: ref er to figure 12-1 f or load conditions . osc1 clk out i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old v alue ne w v alue
1998 microchip technology inc. preliminary ds40181b -page 93 pic12ce67x figure 12-4: r eset, w atc hdog timer , oscillator star t-up timer , and p o wer -up timer timing t ab le 12-5: r eset, w atc hdog timer , oscillator star t-up timer , p o wer -up timer p arameter no. sym characteristic min t yp? max units conditions 30 tmcl mclr pulse width (lo w) 2 m s v dd = 5v , ?0? c to +125?c 31* t wdt w atchdog timer time-out p er iod (no prescaler) 7 18 33 ms v dd = 5v , ?0? c to +125?c 32 t ost oscillation star t-up timer p er iod 1024 t osc t osc = osc1 per iod 33* tpwr t p o w er up timer p er iod 28 72 132 ms v dd = 5v , ?0? c to +125?c 34 t ioz i/o hi -im pedance from mclr lo w or w atchdog timer reset 2 .1 m s * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. v dd mclr inter nal por pwr t timeout osc timeout inter nal reset w atchdog timer reset 33 32 30 31 34 i/o pins 34 3 6
pic12ce67x ds40181b -page 94 preliminary 1998 microchip technology inc. figure 12-5: timer0 cl oc k timings t ab le 12-6: timer0 cloc k requirements t ab le 12-7: gpio p ull-up resistor rang es p aram n o. sym characteristic min t yp? max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20* ns with prescaler 10* ns 41 tt0l t0cki lo w pulse width no prescaler 0.5 t cy + 20* ns with prescaler 10* ns 42 tt0p t0cki p er iod greater of: 20 m s or t cy + 40 * n ns n = prescale v alue ( 1, 2, 4, . .., 256) 48 tc k e2tmri dela y from e xter nal cloc k edge to timer increment 2t osc 7t osc * these par ameters are char acter iz ed b ut not tested. ? data in "t yp" column is at 5v , 25 c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. v dd (v olts) t emperature ( c) min t yp max units gp0/gp1 2.5 ?0 38k 42k 63k w 25 42k 48k 63k w 85 42k 49k 63k w 125 50k 55k 63k w 5.5 ?0 15k 17k 20k w 25 18k 20k 23k w 85 19k 22k 25k w 125 22k 24k 28k w gp3 2.5 ?0 285k 346k 417k w 25 343k 414k 532k w 85 368k 457k 532k w 125 431k 504k 593k w 5.5 ?0 247k 292k 360k w 25 288k 341k 437k w 85 306k 371k 448k w 125 351k 407k 500k w * these par ameters are char acter iz ed b ut not tested. note: ref er to figure 12-1 f or load conditions . 41 42 40 gp2/t0cki tmr 0
1998 microchip technology inc. preliminary ds40181b -page 95 pic12ce67x t ab le 12-8: a/d con ver ter characteristics: pic12ce673-04 (commer cial, industrial, extended (3) ) pic12ce673-10 (commer cial, industrial, extended (3) ) pic12ce674-04 (commer cial, industrial, extended (3) ) pic12ce674-10 (commer cial, industrial, extended (3) ) p arameter no. sym characteristic min t yp? max units conditions n r resolution 8 -b its v ref = v dd = 5.12v, v ss a in v ref (notes 4,5) n int integ r al error less than 1 lsb v ref = v dd = 5.12v, v ss a in v ref (notes 4,5) n dif diff erential error less than 1 lsb v ref = v dd = 5.12v, v ss a in v ref (notes 4,5) n fs full scale error less than 1 lsb v ref = v dd = 5.12v, v ss a in v ref (notes 4,5) n off offset error less than 1 lsb v ref = v dd = 5.12v, v ss a in v ref (notes 4,5 ) monotonicity t yp v ss a in v ref v ref ref erence v oltage 3.0v v dd + 0.3 v v ain analog input v oltage v ss - 0.3 v ref + 0.3 v z ain recommended impedance of analog v oltage source 10.0 k w i ad a/d con v ersion cur- rent ( v dd ) 180 m a a v er age current consumption when a/d is on. (note 1) i ref v ref input current (note 2) 1 10 ma m a dur ing sampling all other times * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. note 1: when a/d is off , it will not consume an y current other than minor leakage current. t he po w er -d o wn current spec includes an y such leakage from the a/d module . 2: v ref current is from gp1 p in or v dd pin, whiche v er is selected as ref erence input. 3: extended oper ating r ange is adv ance inf or mation f or this de vice . 4: these speci cations apply if v ref = 3.0v and if v dd 3 3.0v . v in m ust be betw een v ss and v ref 5: when using e xter nal v ref , v dd m ust be g reater than 3v f or + 1 lsb accur acy . if v dd is less than 3v , y ou m ust use inter nal v ref f or + 1 lsb .
pic12ce67x ds40181b -page 96 preliminary 1998 microchip technology inc. t ab le 12-9: a/d con ver ter characteristics: pic12lce673-04 (commer cial, industrial) pic12lce674-04 (commer cial, industrial) p arameter no. sym characteristic min t yp? max units conditions n r resolution 8 -b its v ref = v dd = 3.0v (note s 1 ,4 ) n int integ r al error less than 1 l sb v ref = v dd = 3.0v (note s 1 ,4 ) n dif diff erential error less than 1 l sb v ref = v dd = 3.0v (note s 1 ,4 ) n fs full scale error less than 1 l sb v ref = v dd = 3.0v (note s 1 ,4 ) n off offset error less than 1 l sb v ref = v dd = 3.0v (note s 1 ,4 ) monotonicity t yp v ss a in v ref v ref ref erence v oltage tbd v dd + 0.3 v v ain analog input v oltage v ss - 0.3 v ref + 0.3 v z ain recommended impedance of ana- log v oltage source 10.0 k w i ad a/d con v ersion cur- rent ( v dd ) tbd m a a v er age current consumption when a/d is on. (note 2) i ref v ref input current (note 3) tbd tbd ma m a dur ing sampling all other times * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. note 1: these speci cations apply if v ref = 3.0v and if v dd 3 3.0v . v in m ust be betw een v ss and v ref 2: when a/d is off , it will not consume an y current other than minor leakage current. t he po w er -d o wn current spec includes an y such leakage from the a/d module . 3: v ref current is from gp1 pin or v dd pin, whiche v er is selected as ref erence input. 4: when using e xter nal v ref , v dd m ust be g reater than 3v f or + 1 lsb accur acy . if v dd is less than 3v , y ou m ust use inter nal v ref f or + 1 lsb .
1998 microchip technology inc. preliminary ds40181b -page 97 pic12ce67x figure 12-6: a/d con ver sion timing t ab le 12-10: a/d con ver sion requirements p arameter no. sym characteristic min t yp? max units conditions 130 t ad a/d cloc k per iod 1.6 2.0 m s m s v ref 3 3.0v v ref full r ange 130 t ad a/d inter nal rc oscillator source 3.0 6.0 9.0 m s adcs1:adcs0 = 11 (rc oscillator source) pic12lce67x, v dd = 3.0v 2.0 4.0 6.0 m s pic 12ce67x 131 t cnv con v ersion time (not including s/h time). note 1 9.5 t ad 132 t acq acquisition time note 2 20 m s * these par ameters are char acter iz ed b ut not tested. ? data in ? yp column is at 5v , 25 c unless otherwise stated. t hese par ameters are f or design guidance only and are not tested. note 1: adres register ma y be read on the f ollo wing t cy cycle . 131 130 132 bsf adcon 0 , go q4 a/d clk a/d d a t a adres adif go sample old_d a t a sampling st opped done new_d a t a ( t o sc /2) (1) 7 6 5 4 3 2 1 0 note 1: if the a/d cloc k source is selected as rc , a time of t cy is added bef ore the a/d cloc k star ts . this allo ws the sleep instr uction to be e x ecuted. 1 tcy
pic12ce67x ds40181b -page 98 preliminary 1998 microchip technology inc. no tes:
1998 microchip technology inc. preliminary ds40181b -page 99 pic12ce67x 13.0 dc and a c characteristics - pic12ce67x the g r aphs and tab les pro vided in this section are f or design guidance and are not tested. in some g r aphs or tab les the data presented are outside speci ed oper ating r ange (e .g., outside speci ed v dd r ange). this is f or inf or mation only and de vices will oper ate proper ly only within the speci ed r ange . the data presented in this section is a statistical summar y of data collected on units from diff erent lots o v er a per iod of time . ? ypical represents the mean of the distr ib ution while ?ax or ?in represents (mean + 3 s ) and (mean ?3 s ) respectiv ely , where s is standard de viation. figure 13-1: calibrated internal rc frequenc y rang e vs. t emperature (v dd = 5.0v) (internal rc is calibrated to 25 c, 5.0v) figure 13-2: calibrated internal rc frequenc y rang e vs. t emperature (v dd = 3.0v) (internal rc is calibrated to 25 c, 5.0v) t o be determined t o be determined
pic12ce67x ds40181b -page 100 preliminary 1998 microchip technology inc. t ab le 13-1: dynamic i dd (t ypical) - wdt enab led, 25 c figure 13-3: wdt timer time-out p eriod vs . v dd oscillator frequenc y v dd = 2.5v v dd = 5.5v exter nal rc 4 mhz tbd m a* 620 m a* inter nal rc 4 mhz tbd m a 1.1 ma xt 4 mhz tbd m a 775 m a lp 32 khz tbd m a 37 m a *does not include current through e xter nal r&c . 50 45 40 35 30 25 20 15 10 5 2 3 4 5 6 7 v dd (v olts) wdt per iod ( m s) max +125 c max +85 c t yp + 25 c min ? 0 c
1998 microchip technology inc. preliminary ds40181b -page 101 pic12ce67x figure 13-4: i oh vs. v oh , v dd = 2.5 v figure 13-5: i oh vs. v oh , v dd = 3.5 v 500m 1.0 1.5 v oh (v olts) i oh ( ma) 2.0 2.5 0 -1 -2 -3 -4 -5 -6 -7 min +125 c max ? 0 c t yp + 25 c min +85 c 3.0 1.5 v oh (v olts) i oh ( ma) 2.0 2.5 0 -5 -10 -15 -20 .50 -18 -13 -8 -3 min +125 c min +85 c t yp + 25 c max ? 0 c figure 13-6: i ol vs. v ol , v dd = 2.5 v figure 13-7: i ol vs. v ol , v dd = 3.5 v 25 20 15 10 5 0 250.0m 500.0m 1.0 v ol (v olts) i ol ( ma) min + 85 c max ? 0 c t yp + 25 c 0 min +125 c 40 30 20 10 0 .50 .75 1.0 v ol (v olts) i ol ( ma) 0 max ? 0 c t yp + 25 c min + 85 c min +125 c
pic12ce67x ds40181b -page 102 preliminary 1998 microchip technology inc. figure 13-8: i oh vs. v oh , v dd = 5.5 v 3.5 4.0 4.5 v oh (v olts) i oh ( ma) 5.0 5.5 0 -5 -10 -15 -20 -25 -30 min +125 c max ? 0 c t yp + 25 c min +85 c figure 13-9: i ol vs. v ol , v dd = 5.5 v 50 40 30 20 10 0 .50 .75 1.0 v ol (v olts) i ol ( ma) .25 min + 85 c max ? 0 c t yp + 25 c min +125 c
1998 microchip technology inc. preliminary ds40181b -page 103 pic12ce67x 14.0 p ac ka ging inf ormation 14.1 p ac ka g e marking inf ormation leg end: mm...m microchip par t n umber inf or mation xx...x customer speci c inf or mation* aa y ear code (last 2 digits of calendar y ear) bb w eek code (w eek of j an uar y 1 is w eek ?1? c f acility code of the plant at which w af er is man uf actured o = outside v endor c = 5 line s = 6 line h = 8 line d mask re vision n umber e assemb ly code of the plant or countr y of or igin in which par t w as assemb led note : in the e v ent the full microchip par t n umber cannot be mar k ed on one line , it will be carr ied o v er to the ne xt line thus limiting the n umber of a v ailab le char acters f or customer speci c inf or mation. * standard o tp mar king consists of microchip par t n umber , y ear code , w eek code , f acility code , mask re v#, and assemb ly code . f or o tp mar king be y ond this , cer tain pr ice adders apply . please chec k with y our microchip sales of ce . f or qtp de vices , an y special mar king adders are included in qtp pr ice . mmmmmmmm xxxxxcde aabb 8-lead pdip (300 mil) example 8-lead windo w ed cer amic side br az ed (300 mil) example 1 2c e674 04/psaz 9725 c e674 jw mmmmmm mm
pic12ce67x ds40181b -page 104 preliminary 1998 microchip technology inc. p ac ka g e t ype: k04-018 8-lead plastic dual in-line (p) ?300 mil * controlling p ar ameter . ? dimension ?1 does not include dam-bar protr usions . dam-bar protr usions shall not e xceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ?1. dimensions ? and ? do not include mold ash or protr usions . mold ash or protr usions shall not e xceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?. 0.310 0.267 0.245 0.355 0.120 0.005 0.060 0.140 0.006 0.000 0.055 0.014 mold dr aft angle bottom mold dr aft angle t op ov er all ro w spacing radius to radius width molded p ac kage width tip to seating plane base to seating plane t op of lead to seating plane t op to seating plane upper lead width lo w er lead width pcb ro w spacing p ac kage length lead thic kness shoulder radius number of pins pitch eb b a l e1 e d a2 a1 a b b1 ? r c n p dimension limits units min 0.380 0.342 5 5 10 10 15 15 0.130 0.280 0.250 0.370 0.020 0.080 0.150 0.018 0.012 0.005 0.060 0.100 0.300 8 0.292 0.260 0.385 0.140 0.035 0.100 0.160 0.015 0.010 0.065 0.022 9.65 8.67 7.87 5 5 10 10 15 15 7.10 6.35 9.40 3.30 0.51 2.03 3.81 0.29 0.13 1.52 0.46 2.54 7.62 3.05 6.78 6.22 9.02 0.13 1.52 3.56 0.36 0.20 0.00 1.40 3.56 7.42 6.60 9.78 0.89 2.54 4.06 8 0.56 0.38 0.25 1.65 min nom inches* max millimeters nom max n 1 2 r d e c b eb e1 a p a1 l a a2 b b1
1998 microchip technology inc. preliminary ds40181b -page 105 pic12ce67x p ac ka g e t ype: k04-084 8-lead ceramic side braz ed dual in-line with windo w (jw) ?300 mil n 1 2 0.260 0.440 0.161 0.310 0.280 0.510 0.130 0.025 0.103 0.145 0.008 0.050 0.016 0.098 min windo w diameter ov er all ro w spacing p ac kage length tip to seating plane base to seating plane t op of body to seating plane t op to seating plane upper lead width lo w er lead width pcb ro w spacing dimension limits lid length lid width p ac kage width lead thic kness number of pins pitch units t u d w eb e a2 a1 l b a c b1 p n 0.450 0.270 0.520 0.166 0.338 0.290 0.140 0.035 0.123 0.460 0.280 0.171 0.365 0.300 0.530 0.150 0.045 0.143 8 nom 0.018 0.165 0.010 0.055 0.100 0.300 max 0.185 0.012 0.060 0.020 0.102 6.86 11.43 4.22 8.57 7.37 13.21 3.56 0.89 3.12 11.18 6.60 12.95 4.09 7.87 7.11 3.30 0.64 2.62 11.68 7.11 13.46 4.34 9.27 7.62 3.81 1.14 3.63 4.19 0.25 1.40 0.46 2.54 7.62 nom millimeters min 0.41 3.68 0.20 1.27 2.49 max 8 0.51 4.70 0.30 1.52 2.59 d t e u w c eb l a1 b b1 a a2 p inches* * controlling p ar ameter .
pic12ce67x ds40181b -page 106 preliminary 1998 microchip technology inc. no tes:
1998 microchip technology inc. preliminary ds40181b -page 107 pic12ce67x inde x a a/d accuracy/error ............................................................ 43 adcon0 register ....................................................... 37 adif bit ....................................................................... 39 analog input model block diagram ............................. 40 analog-to-digital converter ......................................... 37 configuring analog port pins ...................................... 41 configuring the interrupt ............................................. 39 configuring the module ............................................... 39 connection considerations ......................................... 43 conversion clock ........................................................ 41 conversions ................................................................ 42 converter characteristics ........................................... 95 delays ......................................................................... 40 effects of a reset ........................................................ 43 equations .................................................................... 40 flowchart of a/d operation ......................................... 44 go/ done bit .............................................................. 39 internal sampling switch (rss) impedence ................ 40 operation during sleep .............................................. 43 sampling requirements .............................................. 40 sampling time ............................................................ 40 source impedence ...................................................... 40 time delays ................................................................ 40 transfer function ........................................................ 43 absolute maximum ratings ................................................ 81 addlw instruction ............................................................. 64 addwf instruction ............................................................. 64 adie bit ............................................................................... 18 adif bit ............................................................................... 19 adres register ..................................................... 13, 37, 39 alu ....................................................................................... 7 andlw instruction ............................................................. 64 andwf instruction ............................................................. 64 application notes an546 ......................................................................... 37 an556 ......................................................................... 22 architecture harvard ......................................................................... 7 overview ....................................................................... 7 von neumann ................................................................ 7 assembler mpasm assembler ..................................................... 77 b bcf instruction ................................................................... 65 bit manipulation .................................................................. 62 block diagrams analog input model ..................................................... 40 on-chip reset circuit ................................................. 49 timer0 ......................................................................... 31 timer0/wdt prescaler ............................................... 34 watchdog timer .......................................................... 57 bsf instruction ................................................................... 65 btfsc instruction ............................................................... 65 btfss instruction ............................................................... 66 c c bit ..................................................................................... 15 cal0 bit .............................................................................. 21 cal1 bit .............................................................................. 21 cal2 bit .............................................................................. 21 cal3 bit .............................................................................. 21 calfst bit ......................................................................... 21 call instruction ................................................................. 66 calslw bit ........................................................................ 21 carry bit ................................................................................. 7 clocking scheme ................................................................ 10 clrf instruction ................................................................. 66 clrw instruction ............................................................... 66 clrwdt instruction ........................................................... 67 code examples changing prescaler (timer0 to wdt) ........................ 35 changing prescaler (wdt to timer0) ........................ 35 indirect addressing ..................................................... 23 code protection ............................................................ 45, 59 comf instruction ............................................................... 67 computed goto ............................................................... 22 configuration bits ............................................................... 45 d dc bit .................................................................................. 15 dc characteristics pic12ce673 ............................................................... 83 pic12ce674 ............................................................... 83 decf instruction ................................................................ 67 decfsz instruction ............................................................ 67 development support ..................................................... 3, 75 development tools ............................................................. 75 diagrams - see block diagrams digit carry bit ......................................................................... 7 direct addressing ............................................................... 23 e eeprom peripheral operation .......................................... 27 electrical characteristics pic12ce67x .............................................................. 81 errata ..................................................................................... 2 external brown-out protection circuit ................................. 53 external power-on reset circuit ........................................ 53 f family of devices .................................................................. 4 features ................................................................................ 1 fsr register .......................................................... 13, 14, 23 fuzzy logic dev. system ( fuzzy tech -mp) .................... 77 g general description ............................................................... 3 gie bit ................................................................................. 54 goto instruction ............................................................... 68 gpif bit .............................................................................. 56 gpio ............................................................................. 25, 51 gpio register .................................................................... 13 gppu bit ............................................................................. 16 i i/o interfacing ..................................................................... 25 i/o ports ............................................................................. 25 i/o programming considerations ....................................... 26 icepic low-cost pic16cxxx in-circuit emulator ............ 75 id locations ........................................................................ 45 incf instruction .................................................................. 68 incfsz instruction ............................................................. 68 in-circuit serial programming ...................................... 45, 59 indf register ............................................................... 14, 23 indirect addressing ............................................................. 23 initialization conditions for all registers ............................ 51 instruction cycle ................................................................. 10 instruction flow/pipelining .................................................. 10 instruction format ............................................................... 61 instruction set addlw ....................................................................... 64 addwf ...................................................................... 64
pic12ce67x ds40181b -page 108 preliminary 1998 microchip technology inc. andlw ....................................................................... 64 andwf ....................................................................... 64 bcf ............................................................................. 65 bsf ............................................................................. 65 btfsc ........................................................................ 65 btfss ........................................................................ 66 call ........................................................................... 66 clrf ........................................................................... 66 clrw ......................................................................... 66 clrwdt ..................................................................... 67 comf ......................................................................... 67 decf .......................................................................... 67 decfsz ...................................................................... 67 goto ......................................................................... 68 incf ............................................................................ 68 incfsz ....................................................................... 68 iorlw ........................................................................ 68 iorwf ........................................................................ 69 movf .......................................................................... 69 movlw ...................................................................... 69 movwf ...................................................................... 69 nop ............................................................................ 70 option ...................................................................... 70 retfie ....................................................................... 70 retlw ....................................................................... 70 return ..................................................................... 71 rlf ............................................................................. 71 rrf ............................................................................. 71 sleep ........................................................................ 71 sublw ....................................................................... 72 subwf ....................................................................... 72 swapf ....................................................................... 73 tris ............................................................................ 73 xorlw ....................................................................... 73 xorwf ....................................................................... 73 section ........................................................................ 61 intcon register ................................................................ 17 intedg bit .......................................................................... 16 internal sampling switch (rss) impedence ........................ 40 interrupts ............................................................................. 45 a/d .............................................................................. 54 gp2/int ...................................................................... 54 gpio port ................................................................... 54 section ........................................................................ 54 tmr0 .......................................................................... 56 tmr0 overflow ........................................................... 54 iorlw instruction ............................................................... 68 iorwf instruction ............................................................... 69 irp bit ................................................................................. 15 k keeloq evaluation and programming tools .................... 78 l loading of pc ..................................................................... 22 m mclr ............................................................................ 48, 51 memory data memory .............................................................. 11 program memory ........................................................ 11 program memory map pic12ce67x ....................................................... 11 register file map pic12ce67x ....................................................... 12 movf instruction ................................................................ 69 movlw instruction ............................................................. 69 movwf instruction ............................................................. 69 mplab integrated development environment software .... 77 n nop instruction .................................................................. 70 o opcode ............................................................................... 61 option instruction ............................................................ 70 option register ................................................................ 16 orthogonal ............................................................................ 7 osc selection ..................................................................... 45 osccal register ............................................................... 21 oscillator extrc ....................................................................... 50 hs ............................................................................... 50 intrc ......................................................................... 50 lp ............................................................................... 50 xt ............................................................................... 50 oscillator configurations ..................................................... 46 oscillator types extrc ....................................................................... 46 hs ............................................................................... 46 intrc ......................................................................... 46 lp ............................................................................... 46 xt ............................................................................... 46 p package marking information ........................................... 103 packaging information ...................................................... 103 paging, program memory ................................................... 22 pcl ..................................................................................... 62 pcl register .......................................................... 13, 14, 22 pclath .............................................................................. 51 pclath register ................................................... 13, 14, 22 pcon register ............................................................. 20, 50 pd bit ............................................................................ 15, 48 pic12ce67x dc and ac characteristics .......................... 99 picdem-1 low-cost picmicro demo board ..................... 76 picdem-2 low-cost pic16cxx demo board ................... 76 picdem-3 low-cost pic16cxxx demo board ................ 76 picstart plus entry level development system ......... 75 pie1 register ...................................................................... 18 pinout description pic12ce67x ................................................................ 9 pir1 register ..................................................................... 19 pop .................................................................................... 22 por .................................................................................... 50 oscillator start-up timer (ost) ............................ 45, 50 power control register (pcon) ................................. 50 power-on reset (por) ................................... 45, 50, 51 power-up timer (pwrt) ...................................... 45, 50 power-up-timer (pwrt) ........................................... 50 time-out sequence .................................................... 50 time-out sequence on power-up ............................... 52 to ............................................................................... 48 power .................................................................................. 48 power-down mode (sleep) ............................................... 58 prescaler, switching between timer0 and wdt ................ 35 pro mate ii universal programmer .............................. 75 product identification system - pic12ce67x ................... 113 program branches ................................................................ 7 program memory paging ........................................................................ 22 program memory map pic12ce67x .............................................................. 11 program verification ........................................................... 59 ps0 bit ................................................................................ 16 ps1 bit ................................................................................ 16
1998 microchip technology inc. preliminary ds40181b -page 109 pic12ce67x ps2 bit ................................................................................ 16 psa bit ................................................................................ 16 push .................................................................................. 22 r rc oscillator ....................................................................... 47 read modify write .............................................................. 26 read-modify-write .............................................................. 26 register file ........................................................................ 11 registers map pic12ce67x ...................................................... 12 reset conditions ......................................................... 51 reset ............................................................................. 45, 48 reset conditions for special registers .............................. 51 retfie instruction .............................................................. 70 retlw instruction .............................................................. 70 return instruction ........................................................... 71 rlf instruction .................................................................... 71 rp0 bit .......................................................................... 11, 15 rp1 bit ................................................................................ 15 rrf instruction ................................................................... 71 s seeval evaluation and programming system ............... 77 services one-time-programmable (otp) .................................. 5 quick-turnaround-production (qtp) ............................ 5 serialized quick-turnaround production (sqtp) ......... 5 sfr ..................................................................................... 62 sfr as source/destination ................................................ 62 sleep .......................................................................... 45, 48 sleep instruction ............................................................... 71 software simulator (mplab-sim) ...................................... 77 special features of the cpu .............................................. 45 special function register pic12ce67x ............................................................... 13 special function registers ................................................. 62 special function registers, section ................................... 12 stack ................................................................................... 22 overflows .................................................................... 22 underflow .................................................................... 22 status register ............................................................... 15 sublw instruction .............................................................. 72 subwf instruction ............................................................. 72 swapf instruction .............................................................. 73 t t0cs bit .............................................................................. 16 t ad ...................................................................................... 41 timer0 rtcc .......................................................................... 51 timers timer0 block diagram .................................................... 31 external clock .................................................... 33 external clock timing ........................................ 33 increment delay ................................................. 33 interrupt .............................................................. 31 interrupt timing .................................................. 32 prescaler ............................................................ 34 prescaler block diagram .................................... 34 section ............................................................... 31 switching prescaler assignment ........................ 35 synchronization .................................................. 33 t0cki ................................................................. 33 t0if .................................................................... 56 timing ................................................................. 31 tmr0 interrupt ................................................... 56 timing diagrams a/d conversion .......................................................... 97 clkout and i/o ........................................................ 92 external clock timing ................................................. 90 time-out sequence .................................................... 52 timer0 .................................................................. 31, 94 timer0 interrupt timing .............................................. 32 timer0 with external clock ......................................... 33 wake-up from sleep via interrupt ............................... 59 to bit .................................................................................. 15 tose bit ............................................................................. 16 tris instruction .................................................................. 73 tris register ......................................................... 14, 25, 26 two? complement ................................................................ 7 u uv erasable devices ............................................................. 5 w w register alu ................................................................................ 7 wake-up from sleep ........................................................ 58 watchdog timer (wdt) .................................... 45, 48, 51, 57 wdt ................................................................................... 51 block diagram ............................................................ 57 period ......................................................................... 57 programming considerations ..................................... 57 timeout ....................................................................... 51 www, on-line support ........................................................ 2 x xorlw instruction ............................................................. 73 xorwf instruction ............................................................. 73 z z bit ..................................................................................... 15 zero bit .................................................................................. 7
pic12ce67x ds40181b -page 110 preliminary 1998 microchip technology inc.
1998 microchip technology inc. ds40181b -page 10- 111 pic12ce67x systems inf ormation and upgrade hot line the systems inf or mation and upg r ade line pro vides system users a listing of the latest v ersions of all of microchip's de v elopment systems softw are products . plus , this line pro vides inf or mation on ho w customers can receiv e an y currently a v ailab le upg r ade kits .the hot line numbers are: 1-800-755-2345 f or u .s . and most of canada, and 1-602-786-7302 f or the rest of the w or ld. t rademarks: the microchip name , logo , pic , picst ar t , picmaster and pr o ma te are registered tr ademar ks of microchip t echnology incor por ated in the u .s .a. and other countr ies . picmicro , fle x r om, mplab and fuzzy- lab are tr ademar ks and sqtp is a ser vice mar k of micro- chip in the u .s .a. fuzzy tech is a registered tr ademar k of inf or m softw are cor por ation. ibm, ibm pc-a t are registered tr ademar ks of inter national business machines cor p . p entium is a tr ademar k of intel cor por ation. windo ws is a tr ademar k and ms-dos , microsoft windo ws are registered tr ade- mar ks of microsoft cor por ation. compuser v e is a regis- tered tr ademar k of compuser v e incor por ated. all other tr ademar ks mentioned herein are the proper ty of their respectiv e companies . on-line suppor t microchip pro vides on-line suppor t on the microchip w or ld wide w eb (www) site . the w eb site is used b y microchip as a means to mak e les and inf or mation easily a v ailab le to customers . t o vie w the site , the user m ust ha v e access to the inter net and a w eb bro wser , such as netscape or microsoft explorer . files are also a v ailab le f or ftp do wnload from our ftp site . connecting to the micr oc hip internet w eb site the microchip w eb site is a v ailab le b y using y our f a v or ite inter net bro wser to attach to: www .micr oc hip.com the le tr ansf er site is a v ailab le b y using an ftp ser- vice to connect to: ftp://ftp.futureone .com/pub/micr oc hip the w eb site and le tr ansf er site pro vide a v ar iety of ser vices . users ma y do wnload les f or the latest de v elopment t ools , data sheets , application notes , user's guides , ar ticles and sample prog r ams . a v ar i- ety of microchip speci c b usiness inf or mation is also a v ailab le , including listings of microchip sales of ces , distr ib utors and f actor y representativ es . other data a v ailab le f or consider ation is: latest microchip press releases t echnical suppor t section with f requently ask ed questions design tips de vice err ata job p ostings microchip consultant prog r am member listing links to other useful w eb sites related to microchip products conf erences f or products , de v elopment systems , technical inf or mation and more listing of seminars and e v ents 980106
pic12ce67x ds40181b -page 10- 112 1998 microchip technology inc. reader response it is our intention to pro vide y ou with the best documentation possib le to ensure successful use of y our microchip prod- uct. if y ou wish to pro vide y our comments on organization, clar ity , subject matter , and w a ys in which our documentation can better ser v e y ou, please f ax y our comments to the t echnical pub lications manager at (602) 786-7578. please list the f ollo wing inf or mation, and use this outline to pro vide us with y our comments about this data sheet . 1. what are the best f eatures of this document? 2. ho w does this document meet y our hardw are and softw are de v elopment needs? 3. do y ou nd the organization of this data sheet easy to f ollo w? if not, wh y? 4. what additions to the data sheet do y ou think w ould enhance the str ucture and subject? 5. what deletions from the data sheet could be made without aff ecting the o v er all usefulness? 6. is there an y incorrect or misleading inf or mation (what and where)? 7. ho w w ould y ou impro v e this document? 8. ho w w ould y ou impro v e our softw are , systems , and silicon products? t o: t echnical pub lications manager re: reader response t otal p ages sent f rom: name compan y address city / state / zip / countr y t elephone: (_______) _________ - _________ application (optional): w ould y ou lik e a reply? y n de vice: liter ature number : questions: f ax: (______) _________ - _________ ds40181b pic12ce67x
1998 microchip technology inc. preliminary ds40181b -page 113 pic12ce67x pic12ce67x pr oduct identification system please contact y our local sales of ce f or e xact order ing procedures . sales and suppor t products suppor ted b y a preliminar y data sheet ma y possib ly ha v e an err ata sheet descr ibing minor oper ational diff erences and recommended w or karounds . t o deter mine if an err ata sheet e xists f or a par ticular de vice , please contact one of the f ollo wing: 1. y our local microchip sales of ce . 2. the microchip cor por ate liter ature center u .s . f ax: (602) 786-7277 please specify which de vice , re vision of silicon and data sheet (include liter ature #) y ou are using. f or latest v ersion inf or mation and upg r ade kits f or microchip de v elopment t ools , please call 1-800-755-2345 or 1-602-786-7302. p attern: special requirements p ac ka g e: p = 300 mil pdip jw = 300 mil windo w ed cer amic side br az ed t emperature rang e: - = 0 c to +70 c i = -40 c to +85 c e = -40 c to +125 c frequenc y rang e: 04 = 4 mhz/200 khz 10 = 10 mhz de vice pic12ce673 pic12ce674 pic12lce673 pic12lce674 p ar t no . -xx x /xx xxx examples a) pic12ce673-04/p commercial t emp ., pdip p ac kage , 4 mhz, nor mal v dd limits b) pic12ce673-04i/p industr ial t emp ., pdip p ac kage , 4 mhz, nor mal v dd limits c) pic12ce673-10i/p industr ial t emp ., pdip pac kage , 10 mhz, nor mal v dd limits
pic12ce67x ds40181b -page 114 preliminary 1998 microchip technology inc. no tes:
1998 microchip technology inc. preliminary ds40181b -page 115 pic12ce67x no tes:
inf or mation contained in this pub lication regarding de vice applications and the lik e is intended f or suggestion only and ma y be superseded b y updates . no representation or w arr anty is giv en and no liability is assumed b y microchip t echnology incor por ated with respect to the accur acy or use of such inf or mation, or infr ingement of patents or other intellectual proper ty r ights ar ising from such use or otherwise . use of microchip s products as cr itical components in lif e suppor t systems is not author iz ed e xcept with e xpress wr itten appro v al b y microchip . no licenses are con v e y ed, implicitly or otherwise , under an y intellectual proper ty r ights . the microchip logo and name are registered tr ademar ks of microchip t echnology inc. in the u .s .a. and other countr ies . all r ights reser v ed. all other tr ademar ks mentioned herein are the proper ty of their respectiv e companies . ds40181b -page 116 ? 1998 microchip technology inc. all r ights reser v ed. ? 8/28/98 , microchip t echnology incor por ated, usa. f r ida y , a ugust 28, 1998 pr inted on recycled paper . m americas corporate of ce microchip t echnology inc. 2355 w est chandler blvd. chandler , az 85224-6199 t el: 602-786-7200 f ax: 602-786-7277 t echnical suppor t: 602 786-7627 w eb: http://www .microchip .com atlanta microchip t echnology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 t el: 770-640-0034 f ax: 770-640-0307 boston microchip t echnology inc. 5 mount ro y al a v en ue mar lborough, ma 01752 t el: 508-480-9990 f ax: 508-480-8575 chica go microchip t echnology inc. 333 pierce road, suite 180 itasca, il 60143 t el: 630-285-0071 f ax: 630-285-0075 dallas microchip t echnology inc. 14651 dallas p ar kw a y , suite 816 dallas , tx 75240-8809 t el: 972-991-7177 f ax: 972-991-8588 da yton microchip t echnology inc. t w o prestige place , suite 150 miamisb urg, oh 45342 t el: 937-291-1654 f ax: 937-291-9175 detr oit microchip t echnology inc. 42705 gr and riv er , suite 201 no vi, mi 48375-1727 t el: 248-374-1888 f ax: 248-374-2874 los ang eles microchip t echnology inc. 18201 v on kar man, suite 1090 ir vine , ca 92612 t el: 714-263-1888 f ax: 714-263-1338 ne w y ork microchip t echnology inc. 150 motor p ar kw a y , suite 202 hauppauge , ny 11788 t el: 516-273-5305 f ax: 516-273-5335 san jose microchip t echnology inc. 2107 nor th first street, suite 590 san jose , ca 95131 t el: 408-436-7950 f ax: 408-436-7955 americas (contin ued) t or onto microchip t echnology inc. 5925 air por t road, suite 200 mississauga, ontar io l4v 1w1, canada t el: 905-405-6279 f ax: 905-405-6253 asia/p a cific hong k ong microchip asia p aci c rm 3801b , t o w er t w o metroplaza 223 hing f ong road kw ai f ong, n.t ., hong k ong t el: 852-2-401-1200 f ax: 852-2-401-3431 india microchip t echnology inc. india liaison of ce no . 6, legacy , con v ent road bangalore 560 025, india t el: 91-80-229-0061 f ax: 91-80-229-0062 japan microchip t echnology intl. inc. bene x s-1 6f 3-18-20, shin y ok ohama k ohoku-k u, y ok ohama-shi kanaga w a 222-0033 j apan t el: 81-45-471- 6166 f ax: 81-45-471-6122 k orea microchip t echnology k orea 168-1, y oungbo bldg. 3 floor samsung-dong, kangnam-k u seoul, k orea t el: 82-2-554-7200 f ax: 82-2-558-5934 shanghai microchip t echnology rm 406 shanghai golden br idge bldg. 2077 y an?n road w est, hong qiao distr ict shanghai, prc 200335 t el: 86-21-6275-5700 f ax: 86 21-6275-5060 asia/p a cific (contin ued) singapore microchip t echnology singapore pte ltd. 200 middle road #07-02 pr ime centre singapore 188980 t el: 65-334-8870 f ax: 65-334-8850 t aiwan, r.o .c microchip t echnology t aiw an 10f-1c 207 t ung hua nor th road t aipei, t aiw an, r oc t el: 886-2-2717-7175 f ax: 886-2-2545-0139 eur ope united kingdom ar iz ona microchip t echnology ltd. 505 eskdale road winnersh t r iangle w okingham ber kshire , england rg41 5tu t el: 44-1189-21-5858 f ax: 44-1189-21-5835 france ar iz ona microchip t echnology sarl zone industr ielle de la bonde 2 rue du buisson aux f r aises 91300 massy , f r ance t el: 33-1-69-53-63-20 f ax: 33-1-69-30-90-79 german y ar iz ona microchip t echnology gmbh gusta v-heinemann-ring 125 d-81739 m?chen, ger man y t el: 49-89-627-144 0 f ax: 49-89-627-144-44 ital y ar iz ona microchip t echnology srl centro direzionale colleoni p alazz o t aur us 1 v . le colleoni 1 20041 ag r ate br ianza milan, italy t el: 39-39-6899939 f ax: 39-39-6899883 7/7/98 w orldwide s ales and s ervice microchip receiv ed iso 9001 quality system cer ti cation f or its w or ldwide headquar ters , design, and w af er f abr ication f acilities in j an uar y , 1997. our eld-prog r ammab le picmicro 8-bit mcus , ser ial eepr oms , related specialty memor y products and de v elopment systems conf or m to the str ingent quality standards of the inter national standard organization (iso).

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